Layout Design, Staff Engineer
Originally posted 24 September 2026 by the employer.
Work on memory IP that powers chips across the industry, with a focus on custom layout for SRAM and Register Files.
About the role
This Staff Engineer role focuses on custom memory layout design, specifically for SRAM, Register Files, ROM, and related memory compiler IP blocks.
What you'll do
- Design and own custom layouts from floorplan through final signoff for SRAM, Register Files, ROM, and memory compiler IP blocks.
- Execute and close DRC, LVS, ERC, antenna, density, and reliability checks using Virtuoso and physical verification tools.
- Drive technology node migrations for memory compilers, resolving layout and verification issues with new process rules.
- Collaborate with circuit designers to ensure schematic-layout correlation, device matching, symmetry, and design intent.
- Develop and refine layout methodologies, automation scripts in Tcl, Perl, or Python, and best practices.
- Review layouts, provide technical guidance, and mentor junior engineers on complex layout challenges.
What you'll need
- Bachelor's or Master's degree in Electronics, VLSI, Microelectronics, or a related technical field.
- 8 to 10 years of hands-on experience in custom memory layout design, specifically SRAM, Register Files, ROM, or memory compiler development.
- Strong proficiency with custom layout tools such as Cadence Virtuoso or equivalent platforms.
- Demonstrated expertise in DRC/LVS closure, device matching and symmetry, and analog/custom layout techniques.
- Deep understanding of CMOS layout fundamentals, memory architecture, and FinFET technology nodes.
- Experience with parasitic extraction and physical verification flows.
Skills: custom layout, SRAM, Register Files, DRC/LVS, Cadence Virtuoso, FinFET
This role has been open 10 days — well below the 69-day median for Memory Design roles.
Memory Design · Memory Design
|
Open roles in category
287
|
Median days open
69 d
|
Median salary
$205k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Synopsys | All employers we track in this specialty (287 roles · 29 employers) |
|---|---|---|
| Open roles in this specialty | 27 | 287 |
| Median days open | 49 d | 69 d (−20 d vs this employer) |
| Median salary (USD postings) | — | $205k |
Skills observed across this category: custom layout, SRAM, Register Files, DRC/LVS, Cadence Virtuoso, FinFET
Who's hiring in this category
- Micron Technology · 151 open roles · median 86 d
- Synopsys (this employer) · 27 open roles · median 49 d
- SanDisk · 17 open roles · median 32 d
- Broadcom · 16 open roles · median 50 d
- Qualcomm · 12 open roles · median 149 d
- NVIDIA · 7 open roles · median 59 d
How we counted: 287 open Memory Design (Memory Design) roles from 29 employers tracked in the SemiconductorJobs index, counted 5 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Figures refresh nightly.