Layout Design, Sr Engineer in HCMC
Originally posted 7 June 2026 by the employer.
About the role
This role involves designing and integrating memory leafcell and standard cell layouts, with a focus on optimizing for area, speed, and power across advanced FinFET technology nodes.
What you'll do
- Design and integrate memory leafcell layouts and standard cell layouts using Custom Compiler.
- Run and debug physical verification flows including DRC, LVS, ERC, and antenna checks using ICV.
- Collaborate with circuit designers and verification engineers to ensure layout matches design intent.
- Optimize existing layouts for density and performance.
- Help define layout methodologies that scale across multiple process nodes.
What you'll need
- 2+ years of hands-on experience in custom layout, standard cell layout, or memory layout design.
- Deep familiarity with FinFET technology nodes and associated design rules.
- Proficiency with Custom Compiler and physical verification using ICV, Calibre, or similar platforms.
- Strong skills in DRC, LVS, ERC debugging, including resolving complex violations in hierarchical designs.
- Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, or a related field.
- Experience writing layout automation scripts in Perl, Shell, or TCL.
Skills: layout, FinFET, SRAM, DRC, LVS, Custom Compiler
This role has been open 118 days — well above the 69-day median for Memory Design roles.
Memory Design · Memory Design
|
Open roles in category
287
|
Median days open
69 d
|
Median salary
$205k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Synopsys | All employers we track in this specialty (287 roles · 29 employers) |
|---|---|---|
| Open roles in this specialty | 27 | 287 |
| Median days open | 49 d | 69 d (−20 d vs this employer) |
| Median salary (USD postings) | — | $205k |
Skills observed across this category: layout, FinFET, SRAM, DRC, LVS, Custom Compiler
Who's hiring in this category
- Micron Technology · 151 open roles · median 86 d
- Synopsys (this employer) · 27 open roles · median 49 d
- SanDisk · 17 open roles · median 32 d
- Broadcom · 16 open roles · median 50 d
- Qualcomm · 12 open roles · median 149 d
- NVIDIA · 7 open roles · median 59 d
How we counted: 287 open Memory Design (Memory Design) roles from 29 employers tracked in the SemiconductorJobs index, counted 5 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Figures refresh nightly.