Junior Design Verification Engineer, Amazon Leo - Austin, Texas, United States
Originally posted 16 September 2026 by the employer.
Be part of Leo's sub-team responsible for defining and implementing the digital chip SOCs for communications via Low Earth Orbit satellites and Amazon gateways.
About the role
This role involves defining and implementing digital chip SOCs for communications via Low Earth Orbit satellites and Amazon gateways. This is an opportunity to define a groundbreaking wireless solution.
What you'll do
- Develop detailed test plans and write tests, run regressions, collect coverage matrices and report progress to the program.
- Participate in the validation of ASIC implementations in Verilog/SystemVerilog.
- Work with the design and communication systems team and participate in system level verification using test benches constructed using UVM.
- Develop a highly automated environment to run regressions that can be used to make builds and maintain organization of the database.
What you'll need
- Experience with verification environment.
- Ability to develop detailed test plans.
- Experience with Verilog/SystemVerilog.
- Knowledge of UVM.
- Experience with running regressions and collecting coverage matrices.
Skills: verification environment, test plans, UVM, SystemVerilog, regressions, coverage
This role has been open 27 days — well below the 64-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1187
|
Median days open
64 d
|
Median salary
$187k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Amazon | All employers we track in this specialty (1187 roles · 95 employers) |
|---|---|---|
| Open roles in this specialty | 15 | 1187 |
| Open roles in the wider Digital Design & Verification family | 28 | 3167 · 115 employers |
| Median days open | 42 d | 64 d (−22 d vs this employer) |
| Median salary (USD postings) | — | $187k |
Skills observed across this category: verification environment, test plans, UVM, SystemVerilog, regressions, coverage
Who's hiring in this category
- Qualcomm · 103 open roles · median 42 d
- AMD · 99 open roles · median 54 d
- NVIDIA · 79 open roles · median 61 d
- Synopsys · 61 open roles · median 30 d
- SiFive · 54 open roles · median 71 d
- Cadence Design Systems · 51 open roles · median 113 d
How we counted: 1187 open Design Verification (Design Verification) roles from 95 employers tracked in the SemiconductorJobs index, counted 14 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.