IP Verification Engineer - CA, San Jose, United States
Originally posted 18 August 2026 by the employer.
Verify PCIe and CXL based IPs using SystemVerilog and UVM testbenches.
About the role
As an IP Verification Engineer, you will verify FPGA and ASIC designs as part of the front-end design and integration team, collaborating with architecture, IP design, physical design, and product engineering teams. Your focus includes verification of PCIe and CXL based IPs.
What you'll do
- Collaborate with architects, hardware engineers, and firmware engineers to understand new features to be verified for PCIe CXL based IPs. - Develop test plan documentation, accounting for interactions with other features, hardware, firmware, and software driver use cases. - Code IP or subsystem level UVM based testbenches and verification components, including monitors, scoreboards, and checkers. - Build directed and random verification tests. - Run regressions and debug test failures to ensure functional, performance, and implementation quality.
What you'll need
- Bachelors or Masters degree in computer engineering or Electrical Engineering. - Experience with PCIe or CXL or NVMe or ethernet protocols. - Proficiency in IP level ASIC verification. - Expertise in Verilog, System Verilog, and Object Oriented programming. - Expertise in developing UVM based verification frameworks and testbenches. - Experience scripting and maintaining verification processes and flows using python or perl.
Nice to have
- Exposure to leadership or mentorship. - Experience working through the ASIC / FPGA project lifecycle from planning to tape out. - Exposure to simulation profile, efficiency improvement, acceleration, or HLS tools/processes. - Knowledge of computer architecture and systems. - Exposure to generative AI or simulation tools for test, testbench, assertion, test plan generation, or performance optimization.
Skills: ASIC Verification Engineer, PCIe, CXL, UVM based testbenches, System Verilog
This role has been open 69 days — slightly above the 66-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1254
|
Median days open
66 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | AMD | All employers we track in this specialty (1254 roles · 96 employers) |
|---|---|---|
| Open roles in this specialty | 92 | 1254 |
| Open roles in the wider Digital Design & Verification family | 251 | 3346 · 116 employers |
| Median days open | 56 d | 66 d (−10 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: ASIC Verification Engineer, PCIe, CXL, UVM based testbenches, System Verilog
Who's hiring in this category
- Qualcomm · 118 open roles · median 45 d
- AMD (this employer) · 92 open roles · median 55 d
- NVIDIA · 91 open roles · median 65 d
- Synopsys · 65 open roles · median 41 d
- SiFive · 55 open roles · median 83 d
- Cadence Design Systems · 52 open roles · median 125 d
How we counted: 1254 open Design Verification (Design Verification) roles from 96 employers tracked in the SemiconductorJobs index, counted 26 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.