IP Logic Design Engineer - San Jose, United States
$105,440 - $164,800 USD yearly
Originally posted 14 September 2026 by the employer.
This role focuses on 3D NAND flash memory technology.
About the role
This role involves architecting, designing, and verifying logic and circuit blocks for 3D NAND flash memory components. You will contribute to next-gen 3D NAND architecture and pathfinding.
What you'll do
- Architect, design, and verify logic and circuit blocks for 3D NAND flash memory components.
- Define micro-architecture specifications, implement RTL in SystemVerilog, generate synthesis netlists, perform static timing analysis, and drive design sign-off.
- Develop and optimize microcode-based 3D NAND algorithms.
- Collaborate with pre-silicon verification teams to build unit-level test benches, implement SystemVerilog Assertions (SVAs), and run full-chip RTL and gate-level simulation (GLS) regressions.
- Support post-silicon debug and failure analysis.
What you'll need
- MS in electrical or computer engineering with 7+ years of experience, or BS with 9+ years of experience.
- Expertise in Verilog and SystemVerilog.
- Deep understanding of ASIC design flow: RTL design, logic synthesis, STA, ECO.
- Experience with lint tools, CDC/RDC analysis, and timing constraints.
- Strong background in design verification tools and automation scripting.
Nice to have
- Prior experience in 3D NAND Flash Memory logic design.
Skills: 3D NAND flash memory, RTL in SystemVerilog, synthesis, static timing analysis, post-silicon debug
This role has been open 20 days — well below the 69-day median for Memory Design roles.
Memory Design · Memory Design
|
Open roles in category
287
|
Median days open
69 d
|
Median salary
$205k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Solidigm | All employers we track in this specialty (287 roles · 29 employers) |
|---|---|---|
| Open roles in this specialty | 5 | 287 |
| Median days open | 27 d | 69 d (−42 d vs this employer) |
| Median salary (USD postings) | — | $205k |
Skills observed across this category: 3D NAND flash memory, RTL in SystemVerilog, synthesis, static timing analysis, post-silicon debug
Who's hiring in this category
- Micron Technology · 151 open roles · median 86 d
- Synopsys · 27 open roles · median 49 d
- SanDisk · 17 open roles · median 32 d
- Broadcom · 16 open roles · median 50 d
- Qualcomm · 12 open roles · median 149 d
- NVIDIA · 7 open roles · median 59 d
How we counted: 287 open Memory Design (Memory Design) roles from 29 employers tracked in the SemiconductorJobs index, counted 5 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Figures refresh nightly.