IP, EDA and SoC Ecosystem Manager
This role focuses on operational threads connecting strategic initiatives to customers and the semiconductor ecosystem, from idea to silicon.
About the role
This role involves sitting at the intersection of silicon, ecosystem, and customer success, owning the operational thread that connects strategic initiatives to customers and the semiconductor ecosystem.
What you'll do
- Manage all active customer engagements end-to-end, including architectural spec alignment, tape-out, KGD testing, packaging, and volume shipment milestones.
- Ensure alignment with ecosystem partners, including foundries, OSAT/packaging houses, EDA vendors, and IP partners.
- Translate customer requirements (silicon architecture, interface specs, package form factor, delivery schedules) into internal program plans with clear owners and dates.
- Build and maintain program trackers, risk registers, and executive dashboards covering each engagement.
- Drive gate reviews and weekly program syncs across internal RTL/DV, physical design, and validation teams.
- Identify and escalate risks early; propose and implement mitigations before they become schedule threats.
What you'll need
- 15+ years of technical ecosystem management experience in semiconductor, custom silicon, or chiplet/advanced packaging environments.
- Direct experience interfacing with ecosystem partners, including chip development schedules, interdependencies on EDA and IP, tape-out schedules, and silicon bring-up timelines.
- Familiarity with silicon fabrication and advanced packaging formats such as CoWoS, InFO, and 2.5D/3D integration.
- Technical fluency in SoC or chiplet design flows to understand RTL milestones, DV sign-off, PD handoffs, and silicon bring-up phases.
- Proficiency with program tracking tools and experience building program infrastructure from scratch.
- Familiarity with key connectivity IPs like UCIe, PCIe Gen 5/6/7+, or high-bandwidth D2D interconnect standards.
Nice to have
- Prior experience at a chiplet startup, merchant silicon company, or systems company.
- Background in AI/ML infrastructure silicon, including accelerators, network switches, or CPO-enabled platforms.
- Familiarity with IVR/PMIC integration challenges in advanced packaging.
- Exposure to EDA infrastructure programs (SNPS/CDNS cloud flows).
Skills: tape-out, KGD testing, CoWoS, 2.5D/3D integration, RTL milestones, silicon bring-up
More semiconductor jobs: San Jose jobs
This role has been open 67 days — well above the 54-day median for Technical Program Management roles.
Technical Program Management · SOC Architecture
|
Open roles in category
160
|
Median days open
54 d
|
Category median salary (all employers)
$220k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | TYLsemi | All employers we track in this specialty (160 roles · 48 employers) |
|---|---|---|
| Open roles in this specialty | 2 | 160 |
| Median days open | 54 d | 54 d (same as this employer) |
| Median salary (USD postings) | — | $220k |
Skills observed across this category: tape-out, KGD testing, CoWoS, 2.5D/3D integration, RTL milestones, silicon bring-up
Who's hiring in this category
- NVIDIA · 22 open roles · median 54 d
- Qualcomm · 20 open roles · median 64 d
- AMD · 19 open roles · median 32 d
- Synopsys · 14 open roles · median 53 d
- NXP Semiconductors · 7 open roles · median 48 d
- Arm Holdings · 5 open roles · median 11 d
How we counted: 160 open Technical Program Management (SOC Architecture) roles from 48 employers tracked in the SemiconductorJobs index, counted 8 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Figures refresh nightly.