IP Design Verification Engineer - XBAR IP - Bengaluru, India
Originally posted 6 October 2026 by the employer.
Verify the design and implementation of XBAR IP and memory subsystem units.
About the role
This role involves verifying the ASIC design, architecture, and micro-architecture of memory sub-systems/units. You will contribute to the verification of XBAR IP.
What you'll do
- Verify ASIC design, architecture, and micro-architecture of memory sub-systems/units using advanced verification methodologies. - Define verification scope, develop verification infrastructure, and verify design correctness. - Develop test plans, tests, and verification infrastructure for complex IPs/sub-systems. - Build reusable bus functional models, monitors, checkers, and scoreboards following coverage driven verification methodology. - Work on advanced verification methodologies like SV/UVM. - Perform functional coverage driven verification closure.
What you'll need
- 2+ years of relevant experience. - Experience in verification of complex IPs/units and sub-systems. - Background in verification using random stimulus along with functional coverage and assertion-based verification methodologies. - Expertise in Verilog. - Knowledge in SystemVerilog or UVM.
Skills: UVM, SystemVerilog, functional coverage, assertion-based verification, test plans
This role has been open 0 days — well below the 60-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1200
|
Median days open
60 d
|
Median salary
$188k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | NVIDIA | All employers we track in this specialty (1200 roles · 95 employers) |
|---|---|---|
| Open roles in this specialty | 75 | 1200 |
| Open roles in the wider Digital Design & Verification family | 228 | 3135 · 113 employers |
| Median days open | 60 d | 60 d (same as this employer) |
| Median salary (USD postings) | — | $188k |
Skills observed across this category: UVM, SystemVerilog, functional coverage, assertion-based verification, test plans
Who's hiring in this category
- AMD · 103 open roles · median 46 d
- Qualcomm · 100 open roles · median 47 d
- NVIDIA (this employer) · 77 open roles · median 60 d
- Synopsys · 70 open roles · median 28 d
- SiFive · 56 open roles · median 59 d
- Cadence Design Systems · 52 open roles · median 118 d
How we counted: 1200 open Design Verification (Design Verification) roles from 95 employers tracked in the SemiconductorJobs index, counted 6 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.