Intern - PHY Digital Design & Automation Engineer, HBM - Richardson, TX, United States
Originally posted 14 September 2026 by the employer.
This role focuses on High-Bandwidth Memory (HBM) PHY and IO subsystems.
About the role
This role involves supporting the development of digital design methodologies, automation frameworks, timing analysis flows, and architecture validation solutions for High-Bandwidth Memory (HBM) PHY and IO subsystems. This internship offers hands-on experience in digital design, verification, automation, and timing analysis.
What you'll do
- Support digital design, integration, and timing analysis activities for HBM PHY and IO subsystems, including timing constraint development and timing closure efforts.
- Develop and implement verification solutions using Verilog/SystemVerilog and UVM-based environments, analyze simulation results, and debug functional or timing-related issues.
- Create Python-based automation tools and AI Assisted engineering workflows that leverage Large Language Models (LLMs) and Generative AI technologies to improve engineering efficiency.
- Collaborate with architecture, design, verification, and product engineering teams to evaluate features, validate architectures, and improve design quality metrics.
- Document technical findings and present results through design reviews, engineering discussions, and project presentations.
What you'll need
- Currently pursuing a Master's or Ph.D. degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.
- Demonstrated understanding of digital design concepts including finite state machines (FSMs), pipelining, clock-domain crossing (CDC), timing analysis, and computer architecture.
- Experience with RTL design and verification concepts using Verilog or SystemVerilog.
- Proficiency in Python, C++, or a comparable programming language, and experience working in Linux-based development environments.
Nice to have
- Experience with digital implementation flows, static timing analysis (STA), timing closure methodologies, and timing constraint development.
- Familiarity with UVM-based verification environments and regression infrastructure development.
- Experience using EDA tools from Cadence, Synopsys, Siemens, or equivalent vendors.
- Exposure to automation, software development, data analytics, AI Assisted workflows, Large Language Models (LLMs), or Generative AI-based productivity solutions.
- Coursework, research, or project experience related to VLSI design, digital systems, computer architecture, memory systems, timing analysis, or mixed-signal design environments.
This role has been open 20 days — well below the 62-day median for Digital/RTL Design roles.
Digital/RTL Design · RTL Design
|
Open roles in category
968
|
Median days open
62 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Micron Technology | All employers we track in this specialty (968 roles · 101 employers) |
|---|---|---|
| Open roles in this specialty | 21 | 968 |
| Open roles in the wider Digital Design & Verification family | 103 | 3109 · 114 employers |
| Median days open | 61 d | 62 d (−1 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Who's hiring in this category
- Qualcomm · 139 open roles · median 59 d
- Synopsys · 68 open roles · median 25 d
- AMD · 64 open roles · median 45 d
- NXP Semiconductors · 47 open roles · median 81 d
- Analog Devices · 45 open roles · median 40 d
- NVIDIA · 45 open roles · median 59 d
How we counted: 968 open Digital/RTL Design (RTL Design) roles from 101 employers tracked in the SemiconductorJobs index, counted 5 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.