$50 - $50 USD hourly
Originally posted 5 October 2026 by the employer.
Contribute to the architecture and microarchitecture development of future High Bandwidth Memory (HBM) products.
About the role
This role involves contributing to the architecture and microarchitecture development of future High Bandwidth Memory (HBM) products. You will work on architectural innovation across memory systems, controllers, and interfaces.
What you'll do
- Develop and enhance performance models, simulators, and analytical tools using Python, C++, or similar technologies.
- Analyze workload behavior, simulation results, and architectural data to provide recommendations for HBM product development.
- Collaborate with architecture, design, memory controller, and cross-functional engineering teams to support feature definition, design reviews, specifications, and roadmap development.
What you'll need
- 0-2 years of relevant experience through internships, research, academic projects, publications, or coursework in computer architecture, memory systems, VLSI, or semiconductor design.
- Currently pursuing a Bachelor's, Master's, or PhD degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
- Coursework or project experience in computer architecture, memory hierarchies, DRAM technologies, interconnects, or hardware system design.
- Programming experience with Python and at least one of the following: C++, SystemVerilog, or similar engineering languages.
- Ability to read and interpret technical specifications, standards documentation, datasheets, or hardware interface definitions.
- Experience utilizing AI coding assistants and large language models (LLMs) such as GitHub Copilot, Claude, ChatGPT, or similar technologies.
Nice to have
- Experience with memory or system simulation environments such as Ramulator, DRAMSim, gem5, or related architectural modeling tools.
- Knowledge of HBM, DDR, LPDDR, GDDR, memory controller architectures, or memory subsystem design.
- Familiarity with memory reliability and availability concepts, including ECC, repair mechanisms, refresh algorithms, or RAS features.
- Experience with SystemVerilog, digital design, RTL development, or verification methodologies.
- Experience applying AI tools to software development, data analysis, technical research, document analysis, workflow automation, or agentic engineering workflows.
- Understanding of AI training, inference, accelerator architectures, and the role of HBM in large-scale AI systems.
- Previous internship, research, publication, or project experience related to memory systems, computer architecture, semiconductor design, or SoC development.
Skills: HBM architecture, memory scheduling, DRAM technologies, memory controller, performance models
This role has been open 0 days — well below the 69-day median for Memory Design roles.
Memory Design · Memory Design
|
Open roles in category
287
|
Median days open
69 d
|
Median salary
$205k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Micron Technology | All employers we track in this specialty (287 roles · 29 employers) |
|---|---|---|
| Open roles in this specialty | 156 | 287 |
| Median days open | 87 d | 69 d (+18 d vs this employer) |
| Median salary (USD postings) | — | $205k |
Skills observed across this category: HBM architecture, memory scheduling, DRAM technologies, memory controller, performance models
Who's hiring in this category
- Micron Technology (this employer) · 151 open roles · median 86 d
- Synopsys · 27 open roles · median 49 d
- SanDisk · 17 open roles · median 32 d
- Broadcom · 16 open roles · median 50 d
- Qualcomm · 12 open roles · median 149 d
- NVIDIA · 7 open roles · median 59 d
How we counted: 287 open Memory Design (Memory Design) roles from 29 employers tracked in the SemiconductorJobs index, counted 5 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Figures refresh nightly.