Intern – Memory Systems Architecture & AI - San Jose, CA, United States
$49 - $49 USD yearly
Originally posted 28 September 2026 by the employer.
About the role
What you'll do
- Research and evaluate tiered memory architectures for AI inference and large language model workloads.
- Develop experimental methodologies, models, simulations, and prototypes to analyze memory system performance.
- Investigate memory hierarchy optimizations, data placement strategies, cache management, and memory migration mechanisms.
- Perform quantitative analysis using hardware platforms, simulation environments, and FPGA-based prototypes.
- Document research findings, present technical results, and collaborate with architecture teams.
What you'll need
- 0-2 years of relevant experience in computer architecture, memory systems, AI accelerators, or high-performance computing.
- Currently pursuing a PhD in Computer Engineering, Electrical Engineering, Computer Science, or a related technical field.
- Strong understanding of computer architecture, memory hierarchy design, and system performance analysis.
- Experience with systems programming using C++, Python, or similar programming languages.
- Familiarity with performance modeling, simulation, profiling, benchmarking, or experimental system evaluation methodologies.
- Experience using AI-enabled tools and large language models (LLMs).
Nice to have
- Research experience in memory systems, AI accelerators, GPUs, large-scale inference systems, or high-performance computing architectures.
- Experience developing architectural simulators, analytical models, workload characterization frameworks, or system performance evaluation tools.
- Familiarity with AI inference workloads, large language models, KV cache management, Mixture-of-Experts (MoE) architectures, or memory-centric AI system design.
- Experience with FPGA development, RTL design, High-Level Synthesis (HLS), or hardware prototyping platforms.
- Peer-reviewed publications, conference presentations, patents, or other demonstrated research contributions.
Skills: Tiered memory architectures, AI inference, Large language model workloads, Memory system performance, Architectural trade-offs, High-performance computing
This role has been open 6 days — well below the 75-day median for SoC/Chip Architecture roles.
SoC/Chip Architecture · SOC Architecture
|
Open roles in category
442
|
Median days open
75 d
|
Median salary
$236k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Micron Technology | All employers we track in this specialty (442 roles · 64 employers) |
|---|---|---|
| Open roles in this specialty | 18 | 442 |
| Open roles in the wider Digital Design & Verification family | 103 | 3109 · 114 employers |
| Median days open | 121 d | 75 d (+46 d vs this employer) |
| Median salary (USD postings) | — | $236k |
Skills observed across this category: Tiered memory architectures, AI inference, Large language model workloads, Memory system performance, Architectural trade-offs, High-performance computing
Who's hiring in this category
- Qualcomm · 71 open roles · median 82 d
- NVIDIA · 57 open roles · median 59 d
- AMD · 36 open roles · median 61 d
- Arm Holdings · 27 open roles · median 102 d
- Renesas Electronics · 22 open roles · median 59 d
- NXP Semiconductors · 20 open roles · median 104 d
How we counted: 442 open SoC/Chip Architecture (SOC Architecture) roles from 64 employers tracked in the SemiconductorJobs index, counted 5 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.