Intern - Engineering (ASIC Verification) - CA - San Jose - 3870 N. First St, United States
$19 - $30 USD yearly
Originally posted 8 September 2026 by the employer. Relisted by the employer on 21 October 2026.
About the role
As an ASIC Verification Engineering Intern in the Data Center Solutions group (DCS), you will work on developing and validating Data Center Storage products, including enterprise class NVMe SSD controllers and other PCIe-based products. This involves verification at the IP level, subsystem, or SOC level.
What you'll do
- Ramp up on storage-related technical concepts including ARM, AXI, PCIe, NVMe, DDR, NAND Flash, DMA, and encryption. - Work in the SOC verification environment to debug and root-cause failures in SOC. - Write Embedded C programming code and run testcases. - Work with verification environments using UVM testbench. - Run and develop Python, TCL, and Shell verification scripts to test the SOC verification under guidance of the technical lead.
What you'll need
- Actively pursuing a BS degree in Electrical Engineering (MS degree preferred). - Completed coursework in digital design, computer architecture, and C programming. - Proficiency in Verilog or SystemVerilog, C programming, and TCL, Python, or Shell scripting. - Analytical, programming, debugging, and scripting skills.
Nice to have
- Experience with simulation, UVM, and simulation tools.
Skills: ASIC Verification, UVM testbench, SystemVerilog, SOC verification, NAND Flash
This role has been open 43 days — well below the 64-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1220
|
Median days open
64 d
|
Median salary
$186k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Microchip Technology | All employers we track in this specialty (1220 roles · 97 employers) |
|---|---|---|
| Open roles in this specialty | 23 | 1220 |
| Open roles in the wider Digital Design & Verification family | 67 | 3283 · 116 employers |
| Median days open | 70 d | 64 d (+6 d vs this employer) |
| Median salary (USD postings) | — | $186k |
Skills observed across this category: ASIC Verification, UVM testbench, SystemVerilog, SOC verification, NAND Flash
Who's hiring in this category
- Qualcomm · 114 open roles · median 41 d
- AMD · 94 open roles · median 52 d
- NVIDIA · 85 open roles · median 62 d
- Synopsys · 65 open roles · median 36 d
- SiFive · 55 open roles · median 78 d
- Cadence Design Systems · 50 open roles · median 120 d
How we counted: 1220 open Design Verification (Design Verification) roles from 97 employers tracked in the SemiconductorJobs index, counted 21 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.