Intern - DRAM Technology DTCO & PPA Assessment Engineer - Boise, ID - Main Site, United States
Digital Design & SoC Architecture
Originally posted 1 September 2026 by the employer.
About the role
What you'll do
- Evaluate emerging DRAM technologies and analyze their impact on future product architectures and design tradeoffs.
- Perform transistor-level simulations and circuit benchmarking using industry-standard EDA tools such as HSPICE and FineSim.
- Develop and utilize Claude AI-based automation workflows and data analysis processes to improve simulation efficiency and engineering productivity.
- Analyze technical data and communicate insights through presentations and reports that support technology development decisions.
- Collaborate with device engineering, modeling, process integration, and circuit design teams on multi-functional projects.
What you'll need
- Currently pursuing a M.S., or Ph.D. in Electrical Engineering, Computer Engineering, or a related technical field.
- Expected graduation date of Fall 2025 or later.
- Demonstrated knowledge of VLSI design, semiconductor device physics, and CMOS fundamentals.
- Experience with AI-enabled tools, including Claude AI Agents, and data analysis methodologies.
- Familiarity with circuit simulation tools such as HSPICE, FineSim, or equivalent EDA platforms.
Nice to have
- Coursework in CMOS modeling, advanced semiconductor devices, digital circuit design, or semiconductor process technology.
- Experience with scripting languages and automation tools used for engineering workflows.
- Experience applying AI, Agentic AI, or AI-assisted solutions to improve data analysis, simulation, or engineering productivity.
- Exposure to machine learning-based data analysis techniques.
- Experience presenting technical findings and collaborating in multi-functional engineering environments.
Skills: DRAM technologies, transistor-level simulations, HSPICE, FineSim, VLSI design, semiconductor device physics
Market context
This role has been open 33 days — well below the 69-day median for Memory Design roles.
Memory Design · Memory Design
|
Open roles in category
287
|
Median days open
69 d
|
Median salary
$205k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Micron Technology | All employers we track in this specialty (287 roles · 29 employers) |
|---|---|---|
| Open roles in this specialty | 153 | 287 |
| Median days open | 86 d | 69 d (+17 d vs this employer) |
| Median salary (USD postings) | — | $205k |
Skills observed across this category: DRAM technologies, transistor-level simulations, HSPICE, FineSim, VLSI design, semiconductor device physics
Who's hiring in this category
- Micron Technology (this employer) · 151 open roles · median 86 d
- Synopsys · 27 open roles · median 49 d
- SanDisk · 17 open roles · median 32 d
- Broadcom · 16 open roles · median 50 d
- Qualcomm · 12 open roles · median 149 d
- NVIDIA · 7 open roles · median 59 d
How we counted: 287 open Memory Design (Memory Design) roles from 29 employers tracked in the SemiconductorJobs index, counted 5 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Figures refresh nightly.
Boise, ID - Main Site, United States
On-site
Full-time
1 month ago