Intern - DRAM Design Engineer - Boise, ID - Main Site, United States
Originally posted 10 August 2026 by the employer.
This role offers opportunities to employ Artificial Intelligence and AI Assisted tools to improve verification efficiency, analysis, and workflow automation.
About the role
As a DRAM Verification Engineering Intern, you will work within a highly innovative engineering team responsible for verifying advanced memory products. This role also provides opportunities to employ Artificial Intelligence and AI Assisted tools to improve verification efficiency, analysis, and workflow automation.
What you'll do
- Perform verification activities including datasheet analysis, verification planning, simulation execution, coverage analysis, debugging, and results review.
- Support modeling and simulation efforts using industry-standard verification and circuit simulation tools.
- Collaborate with global design, verification, and multi-functional engineering teams to drive standardization and improve design quality.
- Contribute to innovation in future memory technologies by applying advanced verification methodologies.
What you'll need
- Currently pursuing a Bachelor's or Master's degree in Electrical Engineering or a related technical field.
- Must not graduate before September 2026.
- Familiarity with analog and digital simulation tools such as HSPICE, Verilog HDL, FINESIM, or similar industry-standard environments.
- Demonstrated debugging, timing analysis, and analytical skills through coursework, research, or project experience.
Nice to have
- Knowledge of CMOS circuit design, semiconductor devices, and integrated circuit layout concepts.
- Experience with verification, simulation, modeling, or hardware design projects.
- Exposure to DRAM architecture, memory systems, or semiconductor product development.
- Analog IC circuit design coursework or hands-on project experience.
- Experience applying AI, using AI, or leveraging Artificial Intelligence to support engineering workflows, automation, data analysis, or verification productivity improvements.
Skills: DRAM Design Engineer, datasheet analysis, simulation execution, CMOS circuit design, DRAM architecture
This role has been open 55 days — well below the 69-day median for Memory Design roles.
Memory Design · Memory Design
|
Open roles in category
287
|
Median days open
69 d
|
Median salary
$205k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Micron Technology | All employers we track in this specialty (287 roles · 29 employers) |
|---|---|---|
| Open roles in this specialty | 153 | 287 |
| Median days open | 86 d | 69 d (+17 d vs this employer) |
| Median salary (USD postings) | — | $205k |
Skills observed across this category: DRAM Design Engineer, datasheet analysis, simulation execution, CMOS circuit design, DRAM architecture
Who's hiring in this category
- Micron Technology (this employer) · 151 open roles · median 86 d
- Synopsys · 27 open roles · median 49 d
- SanDisk · 17 open roles · median 32 d
- Broadcom · 16 open roles · median 50 d
- Qualcomm · 12 open roles · median 149 d
- NVIDIA · 7 open roles · median 59 d
How we counted: 287 open Memory Design (Memory Design) roles from 29 employers tracked in the SemiconductorJobs index, counted 5 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Figures refresh nightly.