Intern - Digital IP Design Engineer, DRAM - Boise, ID - Main Site, United States
Originally posted 13 August 2026 by the employer.
About the role
As an intern, you will develop and validate digital IP circuits used in future DRAM products. This role focuses on delivering high-quality DRAM IPs that drive product performance and development efficiency.
What you'll do
- Perform circuit analysis across process, voltage, and temperature (PVT) corners to evaluate performance, quality, and reliability. - Develop automation scripts and leverage Agentic AI, AI-Assisted tools, or Code Assist solutions to improve engineering productivity and design quality. - Collaborate with multi-functional engineering teams on design implementation, verification, and silicon validation activities. - Present technical findings, project results, and recommendations to engineering leadership and key customers.
What you'll need
- Currently pursuing a Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Semiconductor Engineering, or a related STEM field. - Completed coursework in CMOS Digital Circuits, SystemVerilog/UVM, and Static Timing Analysis (STA). - Experience with at least one programming language such as Python, Perl, TCL, or MATLAB. - Demonstrated analytical and problem-solving skills through academic, research, or project experience. - Effective written and verbal communication skills with the ability to work in a collaborative team environment.
Nice to have
- Experience with digital IC design, verification, or semiconductor development projects. - Familiarity with RTL design, synthesis, timing closure, verification, and physical design concepts. - Exposure to industry-standard EDA tools used for circuit simulation, verification, and implementation. - Experience applying AI, Generative AI, AI Assistant tools, Agentic AI workflows, or Code Assist technologies to improve engineering processes and development efficiency. - Previous research, internship, or project experience related to memory systems, semiconductor design, or VLSI development.
Skills: DRAM, RTL-to-GDS, SystemVerilog, STA, digital IC design
This role has been open 52 days — well below the 69-day median for Memory Design roles.
Memory Design · Memory Design
|
Open roles in category
287
|
Median days open
69 d
|
Median salary
$205k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Micron Technology | All employers we track in this specialty (287 roles · 29 employers) |
|---|---|---|
| Open roles in this specialty | 153 | 287 |
| Median days open | 86 d | 69 d (+17 d vs this employer) |
| Median salary (USD postings) | — | $205k |
Skills observed across this category: DRAM, RTL-to-GDS, SystemVerilog, STA, digital IC design
Who's hiring in this category
- Micron Technology (this employer) · 151 open roles · median 86 d
- Synopsys · 27 open roles · median 49 d
- SanDisk · 17 open roles · median 32 d
- Broadcom · 16 open roles · median 50 d
- Qualcomm · 12 open roles · median 149 d
- NVIDIA · 7 open roles · median 59 d
How we counted: 287 open Memory Design (Memory Design) roles from 29 employers tracked in the SemiconductorJobs index, counted 5 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Figures refresh nightly.