Intern - Design Architecture, HBM - Richardson, TX, United States
Originally posted 31 August 2026 by the employer. Relisted by the employer on 5 October 2026.
HBM architecture analysis is at the core of this role.
About the role
This role supports early-stage research, performance modeling, and tool development that guide future HBM architectural decisions.
What you'll do
- Research emerging trends in compute, networking, and storage infrastructure to understand how future AI workloads may evolve.
- Support HBM architecture analysis by gathering and synthesizing data related to bandwidth, latency, and system-level memory requirements.
- Help develop or refine simulation frameworks used to model AI cluster performance and memory subsystem behavior.
- Participate in building trend dashboards using CSP benchmarks and industry datasets.
What you'll need
- Currently pursuing a Master’s degree, or a PhD, in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
- Must be able to work onsite for 6-months, and cannot graduate prior to the end of the internship.
- Foundational understanding of computer architecture, digital systems, and hardware/software interaction.
- Programming experience in Python, C/C++ or similar languages.
- Ability to learn new tools, simulation frameworks, and data-analysis workflows.
Nice to have
- Exposure to AI workload behavior, ML training pipelines, or large-scale system bottlenecks.
- Ability to translate research findings into concise technical summaries or recommendations.
- Good understanding of LLMs, Machine learning developments.
Skills: HBM architecture analysis, AI workloads, AI cluster performance, memory subsystem behavior, architectural intercept
This role has been open 44 days — well below the 79-day median for SoC/Chip Architecture roles.
SoC/Chip Architecture · SOC Architecture
|
Open roles in category
453
|
Median days open
79 d
|
Median salary
$233k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Micron Technology | All employers we track in this specialty (453 roles · 63 employers) |
|---|---|---|
| Open roles in this specialty | 19 | 453 |
| Open roles in the wider Digital Design & Verification family | 101 | 3192 · 115 employers |
| Median days open | 134 d | 79 d (+55 d vs this employer) |
| Median salary (USD postings) | — | $233k |
Skills observed across this category: HBM architecture analysis, AI workloads, AI cluster performance, memory subsystem behavior, architectural intercept
Who's hiring in this category
- Qualcomm · 71 open roles · median 85 d
- NVIDIA · 57 open roles · median 68 d
- AMD · 34 open roles · median 63 d
- Apple · 34 open roles · median 8 d
- Arm Holdings · 27 open roles · median 111 d
- NXP Semiconductors · 21 open roles · median 113 d
How we counted: 453 open SoC/Chip Architecture (SOC Architecture) roles from 63 employers tracked in the SemiconductorJobs index, counted 14 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.