$216,400 - $324,600 USD yearly
Originally posted 10 November 2026 by the employer.
About the role
This role implements and directs IP (block/SoC) development for high performance, low power products across ASIC process flows. You will establish implementation strategies spanning synthesis, place and route, timing closure, power analysis, and verification.
What you'll do
- Influence all aspects of the process flow from high-level design to synthesis, place and route, timing, and power use.
- Drive the execution and enablement of architecture and design for blocks, SoC, or IC packages, ensuring resources and procedures are in place.
- Collaborate across functional teams, including software architecture, hardware architecture, product management, and program management, to execute implementation strategies.
- Influence and communicate guidelines for creating advanced architectures, circuit specifications, logic designs, and system simulations.
- Establish guidelines and review technical documentation for EDA, IP, and ASIC projects.
What you'll need
- Bachelor's degree in Science, Engineering, or a related field with 8+ years of ASIC design, verification, validation, integration, or related work experience (or Master's with 7+ years, or PhD with 6+ years).
- Experience leading ASIC implementation across synthesis, place and route, timing, and power optimization.
- Proven experience driving technical execution for block-level and SoC-level development.
Nice to have
- Master's degree in Electrical/Electronic Engineering, Computer Engineering, or Computer Science.
- 12 years of ASIC design, verification, validation, integration, or related work experience.
- 4 years of experience with architecture and design tools.
- 4 years of experience with scripting tools and programming languages.
- 4 years of experience with design verification methods.
- 2 years of experience interacting with senior leadership (e.g., Vice President level and above).
- 1 year of experience working with operating budgets or project financials.
Skills: STA, timing closure, synthesis, place and route, ASIC
More semiconductor jobs: Qualcomm jobs · Physical design jobs · Austin jobs
First seen in our index 0 days ago, well below the 61-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
713
|
Median days since first seen
61 d
|
Category median salary (all employers)
$187k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Qualcomm | All employers we track in this specialty (713 roles · 87 employers) |
|---|---|---|
| Open roles in this specialty | 106 | 713 |
| Open roles in the wider Physical Implementation family | 148 | 1614 · 117 employers |
| Median days since first seen | 61 d | 61 d (same as this employer) |
| Median salary (USD postings) | n/a | $187k |
Skills observed across this category: STA, timing closure, synthesis, place and route, ASIC
Who's hiring in this category
- Qualcomm (this employer) · 104 open roles · median 61 d
- AMD · 62 open roles · median 42 d
- Broadcom · 47 open roles · median 21 d
- NVIDIA · 46 open roles · median 81 d
- Synopsys · 43 open roles · median 40 d
- Intel Corporation · 32 open roles · median 32 d
How we counted: 713 open Physical Design (Physical Design) roles from 87 employers tracked in the SemiconductorJobs index, counted 10 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there, and is counted in the wider Physical Implementation family row. Days are counted from when our index first saw each posting, not from the employer's original posting date.