IC Implementation, Sr Principal AE - San Jose, United States
$148,400 - $275,600 USD yearly
Originally posted 21 October 2026 by the employer.
Drive digital IC implementation and signoff flows at 3nm and below using Cadence digital design tools.
About the role
The Senior Principal Application Engineer drives complex pre-sales and post-sales engagements for Cadence Digital IC products at advanced nodes. The focus spans synthesis, place & route, CTS, floor planning, timing signoff, and power optimization at 3nm and below.
What you'll do
- Lead technical strategy and execution for critical customer design projects, influencing design methodologies and implementation flows at advanced nodes (3nm and below). - Partner with sales teams to grow Cadence business by demonstrating Cadence digital implementation capabilities. - Serve as a primary consultant for advanced-node design synthesis & implementation, Agentic-AI, and signoff, focusing on synthesis, place & route, CTS, floor planning, timing closure, and power optimization. - Develop and deploy custom solutions using scripting languages (TCL, PERL, Python) to address unique customer requirements. - Mentor and guide junior engineers across teams.
What you'll need
- 12+ years of hands-on experience in physical implementation and signoff at 7nm and below, with multiple successful tapeouts. - Demonstrated expertise in digital synthesis, place-and-route, static timing analysis, AI in EDA, and achieving timing and power goals for advanced node designs. - Strong debugging skills with the ability to isolate and resolve critical design issues efficiently. - Proficiency in scripting for automation and flow customization using TCL, PERL, or Python. - Bachelor’s or Master’s in Electrical/Computer Engineering.
Skills: Physical Implementation, Synthesis, Place and Route, Timing Signoff, 3nm, Tcl
This role has been open 1 day — well below the 34-day median for Applications FAE roles.
Applications FAE · EDA Tools
|
Open roles in category
121
|
Median days open
34 d
|
Median salary
$182k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Cadence Design Systems | All employers we track in this specialty (121 roles · 11 employers) |
|---|---|---|
| Open roles in this specialty | 33 | 121 |
| Median days open | 24 d | 34 d (−10 d vs this employer) |
| Median salary (USD postings) | — | $182k |
Skills observed across this category: Physical Implementation, Synthesis, Place and Route, Timing Signoff, 3nm, Tcl
Who's hiring in this category
- Synopsys · 61 open roles · median 31 d
- Cadence Design Systems (this employer) · 33 open roles · median 24 d
- Keysight Technologies · 9 open roles · median 57 d
- Renesas Electronics · 9 open roles · median 70 d
- Amazon · 2 open roles · median 12 d
- Arteris · 2 open roles · median 122 d
How we counted: 121 open Applications FAE (EDA Tools) roles from 11 employers tracked in the SemiconductorJobs index, counted 23 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Figures refresh nightly.