HSIO Validation Engineer - Data Center GPU - TX, Austin, United States
Originally posted 9 September 2026 by the employer.
Work on High Speed IO (HSIO) interfaces crucial to enabling AI-driven processing demands, such as PCIe and AMD Infinity Fabric.
About the role
The HSIO Validation Engineer will work on High Speed IO (HSIO) interfaces that are crucial to enabling AI-driven processing demands, such as PCIe and AMD Infinity Fabric. The scope of work spans pre-silicon readiness, post-silicon bring-up and validation, device interoperability, and customer high volume deployment.
What you'll do
- Develop test procedures for Functional Validation of PCIe Gen5 interface.
- Perform hands-on debug with PCIe state machines, logic analyzers, exercisers, and LTSSM issues.
- Test HSIO performance and power features.
- Implement improvements towards time-to-quality and time-to-root-cause.
- Engage with external partners and customers for tools development and debug.
- Communicate program status through technical reporting.
What you'll need
- Experience with PCIe Gen5 Protocol, Performance, and Power features.
- Experience with SOC digital logic design for link controllers and traffic arbitration.
- Experience with system error handling and management (RAS) for HSIO.
- Experience with HSIO interoperability testing between root, end point, switches, re-timers, and other devices.
- Strong coding skills (Python).
- Bachelor's or Master’s degree in Electrical Engineering (or equivalent field).
Nice to have
- Experience in Data Center Industry.
Skills: HSIO Validation Engineer, PCIe Gen5 Protocol, post-silicon bring-up, logic analyzers, device interoperability
This role has been open 35 days — below the 41-day median for Post-Silicon Validation roles.
Post-Silicon Validation · Silicon Validation
|
Open roles in category
412
|
Median days open
41 d
|
Median salary
$166k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | AMD | All employers we track in this specialty (412 roles · 61 employers) |
|---|---|---|
| Open roles in this specialty | 59 | 412 |
| Open roles in the wider Silicon Validation & Test family | 151 | 2224 · 112 employers |
| Median days open | 41 d | 41 d (same as this employer) |
| Median salary (USD postings) | — | $166k |
Skills observed across this category: HSIO Validation Engineer, PCIe Gen5 Protocol, post-silicon bring-up, logic analyzers, device interoperability
Who's hiring in this category
- AMD (this employer) · 58 open roles · median 41 d
- Micron Technology · 39 open roles · median 37 d
- Qualcomm · 37 open roles · median 27 d
- NVIDIA · 25 open roles · median 22 d
- Graphcore · 21 open roles · median 120 d
- Microchip Technology · 20 open roles · median 70 d
How we counted: 412 open Post-Silicon Validation (Silicon Validation) roles from 61 employers tracked in the SemiconductorJobs index, counted 15 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Silicon Validation & Test family row. Figures refresh nightly.