HBM SoC RTL Design Engineer
Originally posted 21 September 2026 by the employer.
This role focuses on the design, development, and integration of HBM SoC logic die.
About the role
This role involves designing, developing, and integrating HBM SoC logic die, working across architecture, verification, physical design, and firmware teams. You will contribute to robust, high-performance SoC solutions that meet power, performance, and area targets, and enable AI-driven tools and workflows.
What you'll do
- Design and implement RTL for SoC-level blocks and subsystems used in HBM logic die.
- Integrate internal and third-party IP (e.g., controllers, microcontrollers, NOC, RAS, MBIST, interfaces, adapters, buffers, PHY-adjacent logic).
- Collaborate with SoC architects to translate architectural and micro-architectural specifications into high-quality RTL implementations.
- Participate in SoC-level integration activities, including clocking, reset, power intent, and configuration infrastructure.
- Assist with pre-silicon validation and post-silicon bring-up, including root-cause analysis of silicon issues.
- Contribute to design documentation, block specifications, and design reviews.
What you'll need
- Bachelor’s or master’s degree in electrical engineering, computer engineering, or a related field with a minimum of 6 years of experience.
- Proficiency in SystemVerilog/Verilog and familiarity with SoC integration methodologies.
- Experience with the RTL-to-GDS flow, including synthesis, static timing analysis, and develop sign-off considerations.
- Familiarity with EDA tools from Cadence, Synopsys, and/or Siemens.
- Programming or scripting experience (e.g., Python, TCL, Perl, or shell scripting).
Nice to have
- Experience with HBM, DRAM, or memory-centric SoC designs.
- Familiarity with high-speed interfaces, clocking strategies, reset architectures, and power management concepts.
- Exposure to DFT concepts (scan, MBIST, BIRA/BISR) and debug.
- Experience with hardware emulation or acceleration platforms (e.g., Palladium, Veloce, Zebu).
- Understanding of Agentic AI or willingness to learn Agentic AI to help develop efficient workflow.
This role has been open 13 days — well below the 62-day median for Digital/RTL Design roles.
Digital/RTL Design · RTL Design
|
Open roles in category
968
|
Median days open
62 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Micron Technology | All employers we track in this specialty (968 roles · 101 employers) |
|---|---|---|
| Open roles in this specialty | 21 | 968 |
| Open roles in the wider Digital Design & Verification family | 103 | 3109 · 114 employers |
| Median days open | 61 d | 62 d (−1 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Who's hiring in this category
- Qualcomm · 139 open roles · median 59 d
- Synopsys · 68 open roles · median 25 d
- AMD · 64 open roles · median 45 d
- NXP Semiconductors · 47 open roles · median 81 d
- Analog Devices · 45 open roles · median 40 d
- NVIDIA · 45 open roles · median 59 d
How we counted: 968 open Digital/RTL Design (RTL Design) roles from 101 employers tracked in the SemiconductorJobs index, counted 5 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.