HBM Logic Architect - San Jose, CA, United States
$150,000 - $320,000 USD yearly
Originally posted 28 July 2026 by the employer.
About the role
What you'll do
- Define, design, and validate digital IP for ASIC/SoC products.
- Perform RTL design and implementation based on approved specifications.
- Collaborate with cross-functional teams to define IP functionality, behavior, and architecture.
- Review digital IP requirements and evaluate architecture options based on PPA targets.
- Develop and verify RTL designs using industry-standard design methodologies.
- Drive system-level co-optimization beyond standalone DRAM design.
What you'll need
- Bachelor’s degree or higher in Electrical Engineering or a related discipline.
- 5+ years of relevant experience in semiconductor, ASIC/SoC, digital IP, memory, or PHY design.
- High-speed digital PHY or high-speed IP design and analysis.
- DRAM memory controller design and analysis.
- DRAM DFT/DFD architecture, design, or analysis.
- PHY/TSV bit macro design, TSV PHY hard macro design, or 3D PHY design.
Nice to have
- Master’s degree in Electrical Engineering or a related discipline.
- Experience in PPA (Power, Performance, Area) optimization.
Skills: HBM architecture, 3D-stacked DRAM, RTL design, digital IP, memory controller design, DRAM DFT/DFD
This role has been open 68 days — below the 69-day median for Memory Design roles.
Memory Design · Memory Design
|
Open roles in category
287
|
Median days open
69 d
|
Median salary
$205k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | SK Hynix America | All employers we track in this specialty (287 roles · 29 employers) |
|---|---|---|
| Open roles in this specialty | 5 | 287 |
| Median days open | 68 d | 69 d (−1 d vs this employer) |
| Median salary (USD postings) | — | $205k |
Skills observed across this category: HBM architecture, 3D-stacked DRAM, RTL design, digital IP, memory controller design, DRAM DFT/DFD
Who's hiring in this category
- Micron Technology · 151 open roles · median 86 d
- Synopsys · 27 open roles · median 49 d
- SanDisk · 17 open roles · median 32 d
- Broadcom · 16 open roles · median 50 d
- Qualcomm · 12 open roles · median 149 d
- NVIDIA · 7 open roles · median 59 d
How we counted: 287 open Memory Design (Memory Design) roles from 29 employers tracked in the SemiconductorJobs index, counted 5 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Figures refresh nightly.