Lead architecture, feasibility, and system-technology co-optimization (STCO) studies for HBM, stacked DRAM, and hybrid bonding integration.
Originally posted 4 November 2026 by the employer.
About the role
As an HBM Design Architect in the Roadmap and Pathfinding group, you will lead the technical enablement of novel memories and integration technologies grounded in mainstream DRAM and HBM products. You will translate technology capabilities into product architectures, identify critical requirements at risk, and drive de-risking plans across design, process, packaging, and product teams.
What you'll do
- Lead architecture and feasibility assessments for emerging memories, including DRAM, gain cell, and stacked or vertical DRAM, alongside advanced integration techniques such as hybrid bonding and fine-pitch TSV.
- Apply mainstream DRAM and HBM product knowledge across array architecture, timing parameters, bandwidth, power, RAS, and JEDEC requirements to establish product-viable technology criteria.
- Translate device and process characteristics into product-level targets for bandwidth, latency, power, thermals, density, and reliability.
- Define technology targets and execute de-risking plans using test vehicles, DOEs, and modeling or simulation strategies.
- Lead system-technology co-optimization (STCO) studies covering array architecture, periphery/CMOS-under-array, interconnect, PDN, and thermal trade-offs.
- Collaborate with process integration, device, packaging, and design teams to determine technology-to-product intercept points and present roadmap proposals to technical leadership.
What you'll need
- BS in Electrical Engineering, Physics, Materials Science, or a related field with 7+ years of relevant experience; MS with 5+ years; or PhD with 3+ years.
- Grounding in mainstream DRAM or HBM product architecture and design, covering array, periphery, datapath, timing, and power.
- Understanding of DRAM or emerging memory cell and array operation, including sensing, retention, disturb, and variability.
- Working knowledge of semiconductor process technology and its impact on device and circuit behavior.
Nice to have
- PhD or equivalent experience with 10+ years in DRAM/HBM build, memory technology, or pathfinding.
- Direct experience with vertically coordinated DRAM technologies, gain-cell structures (such as 2T0C/IGZO), stacked memory builds, or other emerging memory programs.
- Experience with hybrid bonding, TSV-based 3D integration, or advanced packaging technology development.
Skills: HBM, DRAM, array architecture, hybrid bonding, STCO
More semiconductor jobs: Micron Technology jobs · Richardson jobs
This role has been open 0 days — well below the 70-day median for Memory Design roles.
Memory Design · Memory Design
|
Open roles in category
305
|
Median days open
70 d
|
Category median salary (all employers)
$200k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Micron Technology | All employers we track in this specialty (305 roles · 29 employers) |
|---|---|---|
| Open roles in this specialty | 155 | 305 |
| Median days open | 79 d | 70 d (+9 d vs this employer) |
| Median salary (USD postings) | — | $200k |
Skills observed across this category: HBM, DRAM, array architecture, hybrid bonding, STCO
Who's hiring in this category
- Micron Technology (this employer) · 157 open roles · median 81 d
- Synopsys · 30 open roles · median 75 d
- Qualcomm · 19 open roles · median 96 d
- Broadcom · 16 open roles · median 76 d
- SanDisk · 15 open roles · median 5 d
- NVIDIA · 8 open roles · median 57 d
How we counted: 305 open Memory Design (Memory Design) roles from 29 employers tracked in the SemiconductorJobs index, counted 4 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Figures refresh nightly.