Group Director, Design Engineering - Front End - Austin, United States
Originally posted 24 July 2026 by the employer. Relisted by the employer on 6 October 2026.
About the role
Cadence Solutions (North America) team is looking for a Group Director to lead Front End Design projects.
What you'll do
- Guide and mentor a team of RTL design engineers across front end design projects. - Define and develop microarchitectural features for IPs and subsystems to meet PPA goals. - Write, debug, and optimize RTL code in Verilog, SystemVerilog, or VHDL to create complex digital logic. - Oversee pre-silicon verification activities, including Lint, Clock Domain Crossing (CDC), Formal Verification (FV), and other quality checks. - Work closely with cross-functional teams, including Design Verification (DV), Physical Design (PD), Architecture, and firmware engineers.
What you'll need
- BS or MS in Engineering or Computer Sciences with 10+ years of front end design and/or verification experience. - Experience in leading and managing complex engineering projects within a multi-disciplinary organization. - Experience in IP creation and/or SoC and IP (CPU, Memory, Interface) integration. - Expertise in RTL design (Verilog) along with simulators and debuggers. - Hands-on experience in Synthesis, SDC creation, and supporting PD and STA teams.
Skills: RTL design, Verilog, Synthesis, SDC creation, SoC integration, IP integration
This role has been open 215 days — well above the 66-day median for Digital/RTL Design roles.
Digital/RTL Design · RTL Design
|
Open roles in category
1081
|
Median days open
66 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Cadence Design Systems | All employers we track in this specialty (1081 roles · 104 employers) |
|---|---|---|
| Open roles in this specialty | 19 | 1081 |
| Open roles in the wider Digital Design & Verification family | 121 | 3346 · 116 employers |
| Median days open | 131 d | 66 d (+65 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: RTL design, Verilog, Synthesis, SDC creation, SoC integration, IP integration
Who's hiring in this category
- Qualcomm · 158 open roles · median 63 d
- Synopsys · 86 open roles · median 40 d
- AMD · 77 open roles · median 45 d
- Analog Devices · 49 open roles · median 56 d
- NXP Semiconductors · 44 open roles · median 100 d
- NVIDIA · 37 open roles · median 52 d
How we counted: 1081 open Digital/RTL Design (RTL Design) roles from 104 employers tracked in the SemiconductorJobs index, counted 27 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.