Graduate - Analog Mixed-Signal Design Verification Engineer - Andover, MA
$75,000 - $930,000 USD yearly
Originally posted 9 September 2026 by the employer.
About the role
This role is for a Graduate Analog Mixed-Signal Design Verification Engineer focused on developing verification plans, behavioral models, and testbenches for analog and mixed-signal designs.
What you'll do
- Develop verification plans based on device specifications and requirements to ensure coverage of analog and mixed-signal design intent.
- Generate and maintain Verilog-AMS, SystemVerilog, and mixed-signal behavioral models to support simulation and verification workflows.
- Develop testbenches, simulation environments, and regression flows for mixed-signal verification.
- Create and execute mixed-signal simulation flows to validate device-level and system-level behavior across operating conditions.
- Evaluate behavior under nominal and corner conditions to ensure design robustness and performance compliance.
- Implement fault-injection and stress scenarios to validate error handling and edge-case behavior.
- Run, debug, and maintain regression suites using tools such as Cadence Virtuoso, Cadence vManager, ADE Explorer/Assembler, Spectre, and Xcelium.
What you'll need
- Bachelor's or Master's degree in Electrical Engineering or a related field.
- Experience with analog and mixed-signal verification concepts, testbench creation, and debug practices.
- Experience with Verilog-AMS and SystemVerilog and familiarity with mixed-signal modeling approaches.
- Good understanding of analog design techniques.
- Understanding of hierarchy configurations and mixed-signal netlisting flows.
- US citizen or green card holder status required for access to controlled documentation.
Nice to have
- Exposure to Cadence Virtuoso, Spectre, ADE Explorer/Assembler, vManager, and Xcelium.
- Experience with Python, TCL, or MATLAB for automation, data analysis, or flow enablement.
Skills: Verilog-AMS, SystemVerilog, mixed-signal verification, testbench, Cadence Virtuoso
This role has been open 35 days — well below the 65-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1192
|
Median days open
65 d
|
Median salary
$186k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Infineon Technologies | All employers we track in this specialty (1192 roles · 95 employers) |
|---|---|---|
| Open roles in this specialty | 39 | 1192 |
| Open roles in the wider Digital Design & Verification family | 91 | 3189 · 115 employers |
| Median days open | 63 d | 65 d (−2 d vs this employer) |
| Median salary (USD postings) | — | $186k |
Skills observed across this category: Verilog-AMS, SystemVerilog, mixed-signal verification, testbench, Cadence Virtuoso
Who's hiring in this category
- Qualcomm · 106 open roles · median 42 d
- AMD · 99 open roles · median 55 d
- NVIDIA · 82 open roles · median 57 d
- Synopsys · 63 open roles · median 30 d
- SiFive · 54 open roles · median 72 d
- Cadence Design Systems · 50 open roles · median 114 d
How we counted: 1192 open Design Verification (Design Verification) roles from 95 employers tracked in the SemiconductorJobs index, counted 15 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.