Front-End ASIC Digital Design, Sr. Staff Engineer -18423

Originally posted 21 September 2026 by the employer.

About the role

This role involves owning RTL blocks for high-performance SoCs and driving synthesis and timing closure quality at the front-end boundary from specification through design sign-off.

What you'll do

• Drive front-end sign-off including static timing analysis (STA), lint, CDC/RDC, synthesis, and power efficient design.
• Translate architectural specifications and micro-architecture documents into synthesizable RTL (SystemVerilog/Verilog).
• Own timing constraint (SDC) development and review; support full-chip timing closure.
• Perform synthesis, QoR analysis, and iterative RTL optimization for area, timing, congestion, and power.
• Apply formal property verification (VC Formal) and assertion-based design (SVA) to validate block behavior.
• Run power estimation and analysis (PrimePower) and feed findings back into RTL optimization.

What you'll need

• BS/MS in Electrical/Computer Engineering or a related field, with 8+ years of experience in ASIC design and STA sign-off.
• Demonstrated experience with front-end sign-off flows: STA (PrimeTime), lint (SpyGlass), and CDC/RDC.
• Strong proficiency in SystemVerilog/Verilog RTL coding for synthesis.
• Solid understanding of synthesis (Design Compiler / Fusion Compiler) and QoR analysis.
• Experience with low-power design techniques: clock gating, power gating, multi-Vt, UPF.
• Working knowledge of SDC constraint development and timing closure methodology.
• Proficiency in scripting: TCL, Python, Perl, and Linux/UNIX environments.
• Command of digital design fundamentals: FSMs, arbitration, clock domain crossing, memory interfaces, and standard protocols (AMBA AXI/AHB/APB).
• High-speed interface IP integration experience (PCIe, DDR/LPDDR, Ethernet, USB, MIPI).