FPGA Engineer - Sunnyvale, CA, United States
Originally posted 6 August 2026 by the employer.
This role focuses on the custom RoCE network stack implemented in Cerebras' system and proprietary IOs onto the WSE.
About the role
The Host and Network IO Team develops the full IO path implementation between a distributed system of server nodes, through the cluster, down to the custom RoCE network stack implemented in Cerebras' system, and over the proprietary IOs onto the WSE. As an FPGA developer, you will own the in-chassis IO subsystem consisting of cluster-facing RoCE v2 network interfaces, a large programmable switching fabric, and Serial IO communication with the Cerebras WSE via a proprietary protocol.
What you'll do
- Lead full chassis-to-wafer IO architecture and design
- Improve current RTL, implement next-gen FPGA design, define future IO architectures
- Produce production-ready bitstreams for deployment into large clusters running customer inference services
- Work with DV team to prevent bug slips and simplify debug
- Optimize bandwidth/latency over FPGA datapath and all IO interfaces
- Drive network performance debug of large AI clusters
What you'll need
- 5+ years industry experience generating production FPGA solutions, OR Master's/PhD in Computer or Electrical Engineering + 3 years industry experience
- Proficiency in Verilog development in Git based repo
- Highly productive with FPGA placement & routing, timing closure, simulation, debug, and other FPGA tools/workflows
- Network protocol familiarity (TCP, RoCE) and network debug tools such as Wireshark
- Knowledge of network switch environments
This role has been open 73 days — well above the 61-day median for FPGA Design roles.
FPGA Design · RTL Design
|
Open roles in category
103
|
Median days open
61 d
|
Median salary
$163k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Cerebras | All employers we track in this specialty (103 roles · 26 employers) |
|---|---|---|
| Open roles in this specialty | 1 | 103 |
| Median days open | 73 d | 61 d (+12 d vs this employer) |
| Median salary (USD postings) | — | $163k |
Who's hiring in this category
- Altera · 31 open roles · median 60 d
- AMD · 12 open roles · median 51 d
- Teradyne · 10 open roles · median 70 d
- Qualcomm · 8 open roles · median 42 d
- Microchip Technology · 6 open roles · median 93 d
- Infineon Technologies · 4 open roles · median 38 d
How we counted: 103 open FPGA Design (RTL Design) roles from 26 employers tracked in the SemiconductorJobs index, counted 18 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Figures refresh nightly.