Skip to main content
AMD

FPGA Design and Prototyping Engineer - CA, San Jose, United States

AMD US, CA, San Jose, United States Full-time 17 days ago
Digital Design & SoC Architecture

Originally posted 24 September 2026 by the employer.

Define and own the FPGA prototyping architecture, methodology roadmap, and platform strategy for complex SoCs.

About the role

As a member of the front-end design and integration team, you will help bring silicon designs to life. You will drive FPGA prototyping strategy and execution to enable first-pass silicon success.

What you'll do

  • Define and own the FPGA prototyping architecture, methodology roadmap, and platform strategy for complex SoCs.
  • Lead the development and deployment of FPGA prototype platforms, including RTL adaptation, implementation flows, verification infrastructure, and regression environments.
  • Drive collaboration across Architecture, RTL Design, Verification, Emulation, Software, and Firmware teams.
  • Provide technical leadership for FPGA prototyping engineers through mentoring, design reviews, and best-practice development.
  • Establish engineering processes, implementation methodologies, and documentation standards.
  • Represent the FPGA prototyping organization in architecture reviews, program reviews, and customer-facing technical discussions.

What you'll need

  • 7+ years of experience in FPGA design, implementation, and SoC prototyping.
  • Proven experience leading FPGA prototyping efforts for large-scale semiconductor programs.
  • Strong knowledge of multi-FPGA partitioning, board bring-up, and high-speed interfaces such as PCIe, DDR, Ethernet, USB, and HBM.
  • Deep expertise in FPGA timing closure, floorplanning, CDC analysis, pipelining, and performance optimization.
  • Strong SystemVerilog and/or Verilog design and verification experience.
  • Solid understanding of modern SoC architectures, including CPUs, cache hierarchies, memory subsystems, NoC/interconnects, and I/O protocols such as AXI, ACE, CHI, PCIe, and DDR.

Nice to have

  • Hands-on experience with Synopsys HAPS and/or Cadence Protium platforms.
  • Expert proficiency with AMD/Xilinx Vivado and Vitis toolchains.
Market context

This role has been open 16 days — well below the 60-day median for Digital/RTL Design roles.

Digital/RTL Design · RTL Design

Open roles in category
1019
Median days open
60 d
Median salary
$185k
See the full market breakdown ▾Category comparison, and who else is hiring
How AMD compares in Digital/RTL Design hiring
Metric AMD All employers we track in this specialty (1019 roles · 98 employers)
Open roles in this specialty 75 1019
Open roles in the wider Digital Design & Verification family 265 3166 · 114 employers
Median days open 31 d 60 d (−29 d vs this employer)
Median salary (USD postings) — $185k

Who's hiring in this category

  • Qualcomm · 139 open roles · median 60 d
  • Synopsys · 86 open roles · median 24 d
  • AMD (this employer) · 73 open roles · median 34 d
  • Analog Devices · 50 open roles · median 41 d
  • NXP Semiconductors · 48 open roles · median 78 d
  • NVIDIA · 46 open roles · median 64 d

How we counted: 1019 open Digital/RTL Design (RTL Design) roles from 98 employers tracked in the SemiconductorJobs index, counted 10 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.

Apply now
US, CA, San Jose, United States
On-site
Full-time
17 days ago

Share this job