Foundation IP Memory Verification Engineer - Singapore-Yishun, Singapore
Originally posted 20 August 2026 by the employer.
This role focuses on memory compilers, logic cells, and custom macros on advanced process technology.
About the role
This role is for a Foundation IP Memory Verification Engineer responsible for the development of foundation IP for AI products, including memory compilers, logic cells, and custom macros.
What you'll do
- Contribute towards Memory Design Validation of custom memory macros and memory compilers.
- Perform functional verification, root cause design discrepancies, and help resolve them.
- Perform signal integrity analysis, identify design weaknesses, and propose solutions.
- Perform transistor level simulations to check for Power Up or Lock up issues and help resolve them.
- Perform EM/IR analysis/simulations and evaluate impact on timing and internal margins.
- Perform transistor level simulations to validate timing and internal margins, identify timing characterization holes, and help resolve them.
- Perform QA and validation checks to ensure accurate timing and power models.
- Develop scripts to automate verification flow and data analysis.
- Support silicon debugs and correlation to spice models.
- Collaborate with memory designers to co-develop and improve memory characterization and validation flow.
- Coordinate with memory design leads, modelling leads, and managers to define and execute on the memory validation plan.
What you'll need
- Bachelor's degree in Electronics or Computer Engineering with a minimum of 5 years of memory circuit related experience.
- Understanding of transistor level circuit behavior and device physics.
- Understanding of signal integrity analysis, EM/IR analysis, and reliability analysis.
- Proficiency in running simulators, writing automation scripts, and tools savvy.
Nice to have
- Understanding of memory behavioral and physical models.
- Expertise in memory circuit design.
- Understanding of DFT schemes and chip level integration.
Skills: Memory Design Validation, custom memory macros, memory compilers, transistor level simulations, EM/IR analysis, timing and power models
This role has been open 46 days — well below the 69-day median for Memory Design roles.
Memory Design · Memory Design
|
Open roles in category
287
|
Median days open
69 d
|
Median salary
$205k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Broadcom | All employers we track in this specialty (287 roles · 29 employers) |
|---|---|---|
| Open roles in this specialty | 16 | 287 |
| Median days open | 51 d | 69 d (−18 d vs this employer) |
| Median salary (USD postings) | — | $205k |
Skills observed across this category: Memory Design Validation, custom memory macros, memory compilers, transistor level simulations, EM/IR analysis, timing and power models
Who's hiring in this category
- Micron Technology · 151 open roles · median 86 d
- Synopsys · 27 open roles · median 49 d
- SanDisk · 17 open roles · median 32 d
- Broadcom (this employer) · 16 open roles · median 50 d
- Qualcomm · 12 open roles · median 149 d
- NVIDIA · 7 open roles · median 59 d
How we counted: 287 open Memory Design (Memory Design) roles from 29 employers tracked in the SemiconductorJobs index, counted 5 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Figures refresh nightly.