Foundation IP Development Engineer - Valencia, Cortes Valencianas, Spain
Originally posted 22 September 2026 by the employer.
Develop logic IPs (standard cells and IOs) to support analog, digital, and mixed-signal SOC designs.
About the role
This senior role involves developing logic IPs (standard cells and IOs) to support analog, digital, and mixed-signal SOC designs at various technology nodes.
What you'll do
- Design, simulate, and lay out logic cells and IO circuits.
- Characterize and generate library views for digital, analog, and mixed-signal design and PnR flows.
- Develop and execute library QA methodologies.
- Debug library and design issues.
- Program and script for automation.
What you'll need
- 3+ years of experience with a Master's degree in Electrical Engineering or equivalent.
- Strong knowledge of circuit design, simulations, and characterization.
- Strong knowledge of library view development and verification.
- Familiarity with analog, digital, and mixed-signal design flows.
- Proficiency in programming or scripting.
Skills: logic IPs, standard cells, IO circuit design, library characterization, PnR flows
This role has been open 35 days — well below the 66-day median for Digital/RTL Design roles.
Digital/RTL Design · RTL Design
|
Open roles in category
1081
|
Median days open
66 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Analog Devices | All employers we track in this specialty (1081 roles · 104 employers) |
|---|---|---|
| Open roles in this specialty | 49 | 1081 |
| Open roles in the wider Digital Design & Verification family | 100 | 3328 · 116 employers |
| Median days open | 56 d | 66 d (−10 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: logic IPs, standard cells, IO circuit design, library characterization, PnR flows
Who's hiring in this category
- Qualcomm · 158 open roles · median 63 d
- Synopsys · 86 open roles · median 40 d
- AMD · 77 open roles · median 45 d
- Analog Devices (this employer) · 49 open roles · median 56 d
- NXP Semiconductors · 44 open roles · median 100 d
- NVIDIA · 37 open roles · median 52 d
How we counted: 1081 open Digital/RTL Design (RTL Design) roles from 104 employers tracked in the SemiconductorJobs index, counted 27 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.