Formal Verification Engineer - New College Grad 2026 - CA, Santa Clara, United States
$116,000 - $218,500 USD yearly
Originally posted 13 October 2026 by the employer.
About the role
As a Formal Verification Engineer, you will work in the formal verification team for chips, focusing on the formal verification of RTL units for chip designs.
What you'll do
- Develop comprehensive FV testplan documents.
- Identify key behaviors for verification of DUT and create a verification plan.
- Develop verification environment including environment assumptions, assertions and cover properties.
- Apply various FV techniques to proof correctness of digital designs.
- Debug RTL to identify failure scenarios.
- Develop scripts to automate the verification process.
- Review formal setups and proofs with design and verification teams.
What you'll need
- BS, MS, or Ph.D. in CS/CE/EE/Mathematics or equivalent experience.
- Strong analytical skills to solve difficult problems.
- Knowledge/Experience in formal verification techniques.
- Strong knowledge of architectures of CPU/GPU designs and digital logic.
- Understanding of abstraction techniques for effective verification.
- Hands-on experience with HDLs such as Verilog / System Verilog.
- Ability to understand RTL quickly.
- Understanding of temporal logic assertions.
Skills: formal verification, RTL, SystemVerilog, assertions, FV testplan
This role has been open 0 days — well below the 64-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1187
|
Median days open
64 d
|
Median salary
$187k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | NVIDIA | All employers we track in this specialty (1187 roles · 95 employers) |
|---|---|---|
| Open roles in this specialty | 82 | 1187 |
| Open roles in the wider Digital Design & Verification family | 237 | 3192 · 115 employers |
| Median days open | 56 d | 64 d (−8 d vs this employer) |
| Median salary (USD postings) | — | $187k |
Skills observed across this category: formal verification, RTL, SystemVerilog, assertions, FV testplan
Who's hiring in this category
- Qualcomm · 103 open roles · median 42 d
- AMD · 99 open roles · median 54 d
- NVIDIA (this employer) · 79 open roles · median 61 d
- Synopsys · 61 open roles · median 30 d
- SiFive · 54 open roles · median 71 d
- Cadence Design Systems · 51 open roles · median 113 d
How we counted: 1187 open Design Verification (Design Verification) roles from 95 employers tracked in the SemiconductorJobs index, counted 14 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.