Formal Verification - DV - San Jose, United States
Originally posted 10 June 2026 by the employer.
Drive formal verification across custom IP, compute arrays, NoCs, PCIe, and Ethernet subsystems using JasperGold or VC Formal.
About the role
This role drives formal verification across custom IP, interface IP, and SoC subsystems for ASICs, including compute arrays, DMA engines, NoCs, memory systems, PCIe, and Ethernet. You will partner with architects, RTL designers, DV, and emulation teams to prove design correctness and achieve verification closure.
What you'll do
- Define and execute formal verification plans covering functional correctness, connectivity, ordering, reset behavior, and deadlock/livelock freedom. - Build reusable formal environments using SystemVerilog Assertions, assumptions, constraints, checkers, cut-points, abstraction models, and reference models. - Drive proof convergence using abstractions, cut-points, assume-guarantee reasoning, cover properties, bounded-proof analysis, and coverage metrics. - Translate design intent and specifications into formal properties and closure criteria alongside architects and RTL designers. - Partner with UVM DV, emulation, software, and firmware teams to align formal verification with simulation, coverage, regressions, and bring-up. - Debug RTL, protocol, datapath, connectivity, and integration failures using formal counterexamples, waveforms, and design analysis.
What you'll need
- 5+ years of design verification experience, including hands-on formal verification on complex digital designs or shipping silicon. - Proficiency with SystemVerilog, SystemVerilog Assertions, and formal verification methodology. - Experience with commercial formal tools such as Cadence JasperGold, Synopsys VC Formal, or Siemens Questa Formal. - Understanding of digital design, computer architecture, datapaths, interconnects, memory systems, and standard SoC interfaces. - Ability to model design behavior using assumptions, abstractions, constraints, cut-points, checkers, and reference models.
Skills: formal verification, SystemVerilog Assertions, JasperGold, VC Formal, proof convergence
This role has been open 135 days — well above the 65-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1241
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Median days open
65 d
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Median salary
$185k
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See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Etched | All employers we track in this specialty (1241 roles · 97 employers) |
|---|---|---|
| Open roles in this specialty | 9 | 1241 |
| Open roles in the wider Digital Design & Verification family | 13 | 3322 · 115 employers |
| Median days open | 190 d | 65 d (+125 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: formal verification, SystemVerilog Assertions, JasperGold, VC Formal, proof convergence
Who's hiring in this category
- Qualcomm · 115 open roles · median 42 d
- AMD · 94 open roles · median 52 d
- NVIDIA · 85 open roles · median 64 d
- Synopsys · 66 open roles · median 38 d
- SiFive · 55 open roles · median 80 d
- Cadence Design Systems · 52 open roles · median 122 d
How we counted: 1241 open Design Verification (Design Verification) roles from 97 employers tracked in the SemiconductorJobs index, counted 23 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.