Formal Verification Architect - TX, Austin, United States
Originally posted 10 August 2026 by the employer.
Join the IOHUB team developing I/O connectivity, virtualization, and infrastructure technologies.
About the role
As an ASIC Formal Verification Architect, you will play a critical role in defining and executing formal verification strategies for complex IP and SoC designs. This role is within AMD's NBIO organization, specifically on the IOHUB team, which develops I/O connectivity, virtualization, and infrastructure technologies.
What you'll do
- Lead and mentor a team of formal verification engineers across multiple IP and SoC projects
- Define and drive formal verification architecture, methodologies, and development plans
- Develop comprehensive formal verification test plans and execute verification closure strategies
- Architect, develop, and maintain reusable formal verification environments, properties, components, and infrastructure
- Perform formal connectivity verification, deadlock/livelock analysis, and protocol verification for complex I/O and arbitration-intensive designs
- Debug and triage failures identified through formal verification tools and root-cause complex design issues
What you'll need
- Deep expertise in formal verification methodologies
- Leadership experience guiding technical teams and mentoring engineers
- Experience defining and driving formal verification architecture
- Experience with comprehensive formal verification test plans
- Experience with reusable formal verification environments, properties, components, and infrastructure
- Experience with formal connectivity verification, deadlock/livelock analysis, and protocol verification
- Experience with advanced formal techniques, including abstraction, decomposition, and assume-guarantee methodologies
- BS/MS degree in Engineering (Electrical, Electronics, Computer) or Computer Science
Nice to have
- Strong understanding of digital design and computer architecture
- Verification skills: Formal verification (Static and Dynamic), Assertion based verification, FPV and DPV
- Experience with CDC and RDC formal verification methodologies; proficiency with JasperGold CDC/RDC and Connectivity apps
- Experience with sequential/logical equivalence checking (SEC/LEC)
- Ability to apply abstraction, decomposition, and assume-guarantee reasoning to tackle intractable formal problems at scale
- Strong Design debug, Deep bug hunting skills
- Formal test planning, Formal tools – Jasper, VC-formal
- Design knowledge of CPU, GPU, Bus/Noc/Interconnect, Memory Controllers, Cache
- Familiarity with UVM-based simulation environments and experience bridging formal and simulation-based verification flows
- System Verilog, Verilog or VHDL, Scripting skills
Skills: formal verification, verification strategies, JasperGold, CDC, RDC
This role has been open 69 days — slightly above the 65-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1202
|
Median days open
65 d
|
Median salary
$187k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | AMD | All employers we track in this specialty (1202 roles · 97 employers) |
|---|---|---|
| Open roles in this specialty | 95 | 1202 |
| Open roles in the wider Digital Design & Verification family | 251 | 3201 · 115 employers |
| Median days open | 52 d | 65 d (−13 d vs this employer) |
| Median salary (USD postings) | — | $187k |
Skills observed across this category: formal verification, verification strategies, JasperGold, CDC, RDC
Who's hiring in this category
- Qualcomm · 110 open roles · median 39 d
- AMD (this employer) · 96 open roles · median 51 d
- NVIDIA · 84 open roles · median 59 d
- Synopsys · 64 open roles · median 33 d
- SiFive · 55 open roles · median 75 d
- Cadence Design Systems · 50 open roles · median 117 d
How we counted: 1202 open Design Verification (Design Verification) roles from 97 employers tracked in the SemiconductorJobs index, counted 18 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.