Fabric Modeling and Analysis Engineer for Scale Up Fabric - San Jose, California, United States
$207,000 - $230,000 USD yearly
Originally posted 30 July 2026 by the employer — open 42 days.
About the role
This role involves owning the performance models that shape the Astera Labs Scorpio Scale-Up Fabric, quantifying bandwidth, latency, and throughput, and predicting hardware behavior under real AI/ML workloads.
What you'll do
- Design, implement, and maintain features in AI/ML system simulators and fabric models, extending support for collective communication, transport, topology, congestion, routing, buffering, scheduling, and traffic management.
- Improve simulator fidelity, scalability, debuggability, and runtime performance across packet-level, flow-level, and analytical backends, and build reusable abstractions and APIs for end-to-end simulation flows.
- Calibrate and validate models against benchmark data, owning the correlation between model predictions and measured silicon across scale up fabric generations.
- Design and implement transaction-level or cycle-approximate system models of the Scale up fabric.
- Develop and own theoretical roofline and analytical models that establish bandwidth, latency, and throughput ceilings for the Scale-Up fabric, mapping AI/ML workload demands against fabric capabilities.
Skills: fabric modeling, performance analysis, AI/ML workloads, system simulators, high-speed interconnect
This role has been open 41 days — well below the 69-day median for SoC/Chip Architecture roles.
SoC/Chip Architecture · SOC Architecture
|
Open roles in category
450
|
Median days open
69 d
|
Median salary
$239k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Astera Labs | All employers we track in this specialty (450 roles · 65 employers) |
|---|---|---|
| Open roles in this specialty | 3 | 450 |
| Open roles in the wider Digital Design & Verification family | 40 | 3042 · 114 employers |
| Median days open | 92 d | 69 d (+23 d vs this employer) |
| Median salary (USD postings) | — | $239k |
Skills observed across this category: fabric modeling, performance analysis, AI/ML workloads, system simulators, high-speed interconnect
Who's hiring in this category
- Qualcomm · 68 open roles · median 72 d
- NVIDIA · 54 open roles · median 50 d
- AMD · 32 open roles · median 63 d
- Arm Holdings · 27 open roles · median 77 d
- Renesas Electronics · 20 open roles · median 77 d
- NXP Semiconductors · 18 open roles · median 79 d
How we counted: 450 open SoC/Chip Architecture (SOC Architecture) roles from 65 employers tracked in the SemiconductorJobs index, counted 10 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.