Engineer II - Verification - AZ - Chandler, United States
Originally posted 26 October 2026 by the employer.
About the role
This role is responsible for IP-level verification, testbench architecture, modeling, simulation, coverage, regression, formal or dynamic simulation, debugging, signoff evidence, and lifecycle support within the dsPIC Microcontroller Business Unit.
What you'll do
- Architect, develop, and maintain UVM-based verification environments and Formal verification environments. - Collaborate with architecture, design, validation, and applications teams to verify IP and product requirements. - Develop and maintain verification plans, test strategies, testbenches, constraint random tests, assertions, and coverage metrics. - Develop Formal properties, analyze proof results, and drive Formal coverage closure. - Configure, execute, and maintain UVM simulation and Formal regressions, performing root-cause analysis on failures in RTL and testbenches. - Leverage AI-assisted and machine-learning based automation to improve verification quality and debugging.
What you'll need
- Bachelor’s degree in Electrical Engineering, Electronics Engineering, Computer Engineering, Computer Science, Physics, Engineering, or a related field. - 2.5 to 5 years of relevant experience in design verification, UVM and/or Formal testbench architecture, modeling, simulation, coverage, regression, debugging, signoff evidence, and lifecycle support. - Demonstrated experience in verification architecture, modeling, and simulation across UVM and Formal testbench development. - Background in coverage analysis, structured debugging, AI/ML automation, and technical documentation.
Nice to have
- Hands-on experience with UVM-based simulation and Formal verification methodologies and tools. - Strong proficiency in SystemVerilog language, constrained-random verification, assertions, and coverage. - Experience developing and maintaining IP-level and SoC-level verification environments. - Experience with verification automation and scripting using Python or Perl. - Experience with AI-assisted technologies to improve verification productivity and drive faster coverage closure. - Strong understanding of digital design concepts, RTL fundamentals, and ARM or common SoC architectures.
Skills: UVM, SystemVerilog, Formal verification, coverage closure, testbench
This role has been open 0 days — well below the 66-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1254
|
Median days open
66 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Microchip Technology | All employers we track in this specialty (1254 roles · 96 employers) |
|---|---|---|
| Open roles in this specialty | 22 | 1254 |
| Open roles in the wider Digital Design & Verification family | 66 | 3346 · 116 employers |
| Median days open | 67 d | 66 d (+1 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: UVM, SystemVerilog, Formal verification, coverage closure, testbench
Who's hiring in this category
- Qualcomm · 118 open roles · median 45 d
- AMD · 92 open roles · median 55 d
- NVIDIA · 91 open roles · median 65 d
- Synopsys · 65 open roles · median 41 d
- SiFive · 55 open roles · median 83 d
- Cadence Design Systems · 52 open roles · median 125 d
How we counted: 1254 open Design Verification (Design Verification) roles from 96 employers tracked in the SemiconductorJobs index, counted 26 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.