Emulation Verification Engineer
About the role
As a member of the emulation verification team, you will utilize emulation platforms to verify large wireless SoCs. The scope involves porting designs and mixed-signal models onto the Palladium platform and executing detailed emulation test plans.
What you'll do
- Create, deploy, and support emulation environments for wireless SoC design verification.
- Port designs and mixed-signal models onto the Palladium emulation platform.
- Execute detailed emulation test plans and collaborate across chip design disciplines.
- Perform bring-up, debugging, and verification within emulation flows.
What you'll need
- Bachelor’s degree in a relevant technical field.
- Experience with SystemVerilog, Verilog, or UVM.
Nice to have
- Experience with bring-up, debugging, and verification in emulation.
- Understanding of the tool flow from RTL to emulation.
- Understanding of standard emulator flows (Palladium, Veloce, Zebu) or FPGA flows (Xilinx, Altera).
- Design verification or silicon validation experience.
- Experience writing synthesizable SystemVerilog/Verilog code and SystemVerilog assertions.
- Experience with SystemVerilog verification environments including C/C++ DPI and UVM.
- Scripting experience in Perl, Python, or TCL.
- Hands-on usage of low-power methodologies (UPF-based).
- Experience in UVM Acceleration.
Skills: Emulation, Palladium, Zebu, SystemVerilog, UVM
More semiconductor jobs: Apple jobs · Verification engineer jobs
This role has been open 0 days — well below the 58-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1293
|
Median days open
58 d
|
Category median salary (all employers)
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Apple | All employers we track in this specialty (1293 roles · 99 employers) |
|---|---|---|
| Open roles in this specialty | 93 | 1293 |
| Open roles in the wider Digital Design & Verification family | 176 | 3447 · 120 employers |
| Median days open | 13 d | 58 d (−45 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: Emulation, Palladium, Zebu, SystemVerilog, UVM
Who's hiring in this category
- Qualcomm · 116 open roles · median 48 d
- NVIDIA · 104 open roles · median 70 d
- AMD · 86 open roles · median 64 d
- Apple (this employer) · 75 open roles · median 14 d
- Synopsys · 73 open roles · median 49 d
- SiFive · 60 open roles · median 62 d
How we counted: 1293 open Design Verification (Design Verification) roles from 99 employers tracked in the SemiconductorJobs index, counted 4 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.