Emulation Engineer, Hardware Prototyping (HAPS) - San Jose, United States
$150,000 - $275,000 USD yearly
Originally posted 1 June 2026 by the employer.
About the role
As an Emulation Engineer specializing in Hardware Prototyping (HAPS), you will own prototype bring-up, partitioning RTL, and enabling pre-silicon subsystem configurations for software teams. The work focuses on HAPS hardware prototyping, multi-FPGA timing closure, and interface bring-up for inference systems.
What you'll do
- Own HAPS bring-up by taking RTL from design teams through partitioning, multi-FPGA timing closure, clocking, memory mapping, and full-chip assembly. - Expand platform coverage by standing up new subsystem configurations to enable early firmware, driver, and software execution. - Support firmware, driver, and software users by triaging failures across RTL, software, and prototyping platforms. - Debug multi-FPGA boundary issues using waveform capture, protocol analyzers, and custom tooling. - Bring up interfaces, models, and physical bridges including PCIe, Ethernet, HBM, memory models, JTAG, I2C, UART, and QSPI. - Build and automate flows for builds, regressions, and image delivery.
What you'll need
- Hands-on FPGA prototyping experience covering partitioning, synthesis, timing closure, bring-up, and debug using HAPS, Protium, proFPGA, S2C, or similar systems. - Strong SystemVerilog and Verilog expertise, with knowledge of FPGA synthesis constraints. - Solid C/C++ and Linux system development skills. - Scripting fluency for automation using Python, TCL, and shell.
Skills: SoC bring-up, emulation platforms, pre-silicon validation, DPI transactors, regression flows
This role has been open 144 days — well above the 64-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1254
|
Median days open
64 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Etched | All employers we track in this specialty (1254 roles · 97 employers) |
|---|---|---|
| Open roles in this specialty | 9 | 1254 |
| Open roles in the wider Digital Design & Verification family | 13 | 3322 · 115 employers |
| Median days open | 191 d | 64 d (+127 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: SoC bring-up, emulation platforms, pre-silicon validation, DPI transactors, regression flows
Who's hiring in this category
- Qualcomm · 120 open roles · median 43 d
- AMD · 94 open roles · median 53 d
- NVIDIA · 84 open roles · median 65 d
- Synopsys · 67 open roles · median 39 d
- SiFive · 55 open roles · median 81 d
- Cadence Design Systems · 52 open roles · median 123 d
How we counted: 1254 open Design Verification (Design Verification) roles from 97 employers tracked in the SemiconductorJobs index, counted 24 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.