DRAM Layout engineer (Intern) - Jalisco, Mexico
Originally posted 25 August 2026 by the employer.
About the role
This role involves collaborating with global design, layout, and verification teams to develop high-quality physical layouts for DRAM products. You will gain hands-on experience in semiconductor layout building, physical verification, and industry-standard Electronic Design Automation (EDA) tools.
What you'll do
- Design and verify all levels of analog and digital layout.
- Use computer-aided design software like Cadence.
- Work with Design Engineers to floorplan and design layout.
- Understand and follow verification protocols.
- Apply custom and/or automated layout techniques for pitch, array, and peripheral layout of digital and analog circuits.
- Collaborate with build engineering to understand layout methodology.
What you'll need
- Student pursuing a bachelor's degree (last 2 semesters preferred) in Electrical Engineering, Electronics Engineering, Mechatronics, Robotics, Nanotechnology, Computer Engineering, or a related field.
- Completed coursework or academic projects related to microelectronics, semiconductor devices, VLSI, or integrated circuit design.
- Basic understanding of CMOS technology and layout design principles.
Nice to have
- Strong interest in semiconductor physical design and memory technologies.
- Familiarity with Linux environments and scripting basics.
- Exposure to EDA tools such as Cadence Virtuoso, Synopsys IC Compiler II, Fusion Compiler, or similar tools.
- Experience with programming or scripting languages such as Python, Tcl, Perl, C, or C++.
- Understanding of physical verification concepts (DRC, LVS, ERC).
Skills: DRAM Layout engineer, CMOS technology, layout design principles, physical verification concepts (DRC, LVS, ERC), Cadence Virtuoso, memory technologies
This role has been open 62 days — below the 71-day median for Memory Design roles.
Memory Design · Memory Design
|
Open roles in category
309
|
Median days open
71 d
|
Median salary
$200k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Micron Technology | All employers we track in this specialty (309 roles · 31 employers) |
|---|---|---|
| Open roles in this specialty | 157 | 309 |
| Median days open | 91 d | 71 d (+20 d vs this employer) |
| Median salary (USD postings) | — | $200k |
Skills observed across this category: DRAM Layout engineer, CMOS technology, layout design principles, physical verification concepts (DRC, LVS, ERC), Cadence Virtuoso, memory technologies
Who's hiring in this category
- Micron Technology (this employer) · 157 open roles · median 91 d
- Synopsys · 30 open roles · median 67 d
- Qualcomm · 19 open roles · median 88 d
- Broadcom · 17 open roles · median 68 d
- SanDisk · 17 open roles · median 54 d
- NVIDIA · 7 open roles · median 34 d
How we counted: 309 open Memory Design (Memory Design) roles from 31 employers tracked in the SemiconductorJobs index, counted 27 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Figures refresh nightly.