DRAM Layout engineer (Intern) - Jalisco, Mexico
Originally posted 25 August 2026 by the employer.
About the role
This role involves collaborating with global design, layout, and verification teams to develop high-quality physical layouts for DRAM products. You will gain hands-on experience in semiconductor layout building, physical verification, and industry-standard Electronic Design Automation (EDA) tools.
What you'll do
- Design and verify all levels of analog and digital layout.
- Use computer-aided design software like Cadence.
- Work with Design Engineers to floorplan and design layout.
- Understand and follow verification protocols.
- Apply custom and/or automated layout techniques for pitch, array, and peripheral layout of digital and analog circuits.
- Collaborate with build engineering to understand layout methodology.
What you'll need
- Student pursuing a bachelor's degree (last 2 semesters preferred) in Electrical Engineering, Electronics Engineering, Mechatronics, Robotics, Nanotechnology, Computer Engineering, or a related field.
- Completed coursework or academic projects related to microelectronics, semiconductor devices, VLSI, or integrated circuit design.
- Basic understanding of CMOS technology and layout design principles.
Nice to have
- Strong interest in semiconductor physical design and memory technologies.
- Familiarity with Linux environments and scripting basics.
- Exposure to EDA tools such as Cadence Virtuoso, Synopsys IC Compiler II, Fusion Compiler, or similar tools.
- Experience with programming or scripting languages such as Python, Tcl, Perl, C, or C++.
- Understanding of physical verification concepts (DRC, LVS, ERC).
Skills: DRAM Layout engineer, CMOS technology, layout design principles, physical verification concepts (DRC, LVS, ERC), Cadence Virtuoso, memory technologies
This role has been open 40 days — well below the 69-day median for Memory Design roles.
Memory Design · Memory Design
|
Open roles in category
287
|
Median days open
69 d
|
Median salary
$205k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Micron Technology | All employers we track in this specialty (287 roles · 29 employers) |
|---|---|---|
| Open roles in this specialty | 153 | 287 |
| Median days open | 86 d | 69 d (+17 d vs this employer) |
| Median salary (USD postings) | — | $205k |
Skills observed across this category: DRAM Layout engineer, CMOS technology, layout design principles, physical verification concepts (DRC, LVS, ERC), Cadence Virtuoso, memory technologies
Who's hiring in this category
- Micron Technology (this employer) · 151 open roles · median 86 d
- Synopsys · 27 open roles · median 49 d
- SanDisk · 17 open roles · median 32 d
- Broadcom · 16 open roles · median 50 d
- Qualcomm · 12 open roles · median 149 d
- NVIDIA · 7 open roles · median 59 d
How we counted: 287 open Memory Design (Memory Design) roles from 29 employers tracked in the SemiconductorJobs index, counted 5 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Figures refresh nightly.