DRAM IP Development Layout (Internship) - Jalisco, Mexico
Originally posted 25 August 2026 by the employer.
About the role
This internship involves contributing to the development and verification of selected IP layout cells used in memory products, focusing on industry-standard layout methodologies.
What you'll do
- Develop the layout of selected analog and digital IP layout cells.
- Perform Design Rule Check (DRC) and Layout Versus Schematic (LVS) verification and document findings.
- Create and deliver technical reports summarizing design work, verification results, and key lessons learned.
- Design and implement a SKILL-based automation solution to improve layout design or verification processes.
- Support engineering activities through AI-assisted development methodologies and productivity tools.
What you'll need
- Student pursuing a Bachelor's degree in Electrical Engineering, Electronics Engineering, Mechatronics, Robotics, Nanotechnology, Computer Engineering, or a related field, preferably within the final two semesters of study.
- Expected graduation date of December 2027.
- Experience with at least one scripting language such as Python, Perl, or similar.
Nice to have
- Academic or internship experience related to semiconductor layout design processes.
- Understanding of Design Rule Checks (DRC) and Layout Versus Schematic (LVS) analysis.
- Applying AI applications in semiconductor development.
- Experience using Electronic Design Automation (EDA) tools such as Cadence or Synopsys.
- Interest in semiconductor memory technologies and physical design methodologies.
Skills: DRAM IP, layout, analog and digital IP layout cells, DRC, LVS, Cadence, Synopsys
This role has been open 40 days — well below the 69-day median for Memory Design roles.
Memory Design · Memory Design
|
Open roles in category
287
|
Median days open
69 d
|
Median salary
$205k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Micron Technology | All employers we track in this specialty (287 roles · 29 employers) |
|---|---|---|
| Open roles in this specialty | 153 | 287 |
| Median days open | 86 d | 69 d (+17 d vs this employer) |
| Median salary (USD postings) | — | $205k |
Skills observed across this category: DRAM IP, layout, analog and digital IP layout cells, DRC, LVS, Cadence
Who's hiring in this category
- Micron Technology (this employer) · 151 open roles · median 86 d
- Synopsys · 27 open roles · median 49 d
- SanDisk · 17 open roles · median 32 d
- Broadcom · 16 open roles · median 50 d
- Qualcomm · 12 open roles · median 149 d
- NVIDIA · 7 open roles · median 59 d
How we counted: 287 open Memory Design (Memory Design) roles from 29 employers tracked in the SemiconductorJobs index, counted 5 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Figures refresh nightly.