DRAM Design Technology Layout Engineer - Jalisco, Mexico
Originally posted 21 July 2026 by the employer.
About the role
This role is responsible for translating schematics into layout for fabrication reticules, meeting all engineering and process criteria for an assigned DRAM product. The position involves applying multiple layout techniques for the design and verification of digital and analog circuits.
What you'll do
- Design and develop IP layouts used in DRAM chips.
- Perform layout verification including LVS/DRC/EM, quality checks, and documentation.
- Ensure on-time delivery of block-level layouts with acceptable quality.
- Plan layout details and present material for global team review.
- Communicate with engineering teams to ensure project success.
What you'll need
- Bachelor’s degree or equivalent experience in Electrical, Electronics, Mechatronics, Robotics, Biomedical Engineering or a related field with an electrical engineering background.
- 3+ years of experience in layout designs in advanced CMOS process.
- Ability to perform IP layout development and physical verification for complex designs as per provided specifications.
- Expertise in layout area and routing optimization, design rules, yield, and reliability issues.
- Understanding of layout fundamentals including Electro-migration, Latch-up, coupling, crosstalk, IR-drop, parasitic analysis, matching, shielding.
- Experience with Cadence tools including Virtuoso schematic editor, Virtuoso layout L, XL, and verification tools like Mentor Calibre, proficient in Device Matching, Parasitic Analysis, Electron Migration, and Isolation Techniques.
Nice to have
- Knowledge of Skill coding and layout automation.
Skills: DRAM IP layouts, LVS/DRC/EM, layout optimization, Cadence Virtuoso, Mentor Calibre
This role has been open 136 days — well above the 69-day median for Memory Design roles.
Memory Design · Memory Design
|
Open roles in category
287
|
Median days open
69 d
|
Median salary
$205k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Micron Technology | All employers we track in this specialty (287 roles · 29 employers) |
|---|---|---|
| Open roles in this specialty | 153 | 287 |
| Median days open | 86 d | 69 d (+17 d vs this employer) |
| Median salary (USD postings) | — | $205k |
Skills observed across this category: DRAM IP layouts, LVS/DRC/EM, layout optimization, Cadence Virtuoso, Mentor Calibre
Who's hiring in this category
- Micron Technology (this employer) · 151 open roles · median 86 d
- Synopsys · 27 open roles · median 49 d
- SanDisk · 17 open roles · median 32 d
- Broadcom · 16 open roles · median 50 d
- Qualcomm · 12 open roles · median 149 d
- NVIDIA · 7 open roles · median 59 d
How we counted: 287 open Memory Design (Memory Design) roles from 29 employers tracked in the SemiconductorJobs index, counted 5 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Figures refresh nightly.