Distinguished Engineer (DE) or Senior Director, Central Engineering – SoC Design & Modeling Methodologies
Originally posted 23 October 2026 by the employer.
About the role
This role serves as the technical leader of workload and performance analysis, hardware/software (HW/SW) optimization and co-design (including AI workloads), and SoC architecture across Central Engineering. The scope encompasses workload characterization, performance and power tradeoffs, modeling methodologies, and design enablement strategies across multiple product lines.
What you'll do
- Define and drive the strategic roadmap for workload analysis and performance for IPs and products across the company. - Lead architecture performance reviews and provide technical direction for complex IP/SoC and subsystem developments. - Establish best practices for hardware/software co-design, model-based development, and virtual platforms. - Define and analyze AI workloads and establish the required performance profiles for silicon implementations. - Provide technical leadership across functional teams spanning architecture, design, verification, emulation, and software. - Build and mentor engineering teams, including directors, principal engineers, and distinguished engineers.
What you'll need
- MS or Ph.D. in Electrical Engineering, Computer Engineering, Computer Science, or a related technical discipline. - 15+ years of experience in semiconductor or SoC development, with 8+ years of technical leadership experience. - Proven track record leading performance analysis, workload analysis, and HW/SW co-optimization. - Deep expertise in SoC architecture and integration, digital design methodologies, and IP/subsystem development. - Hands-on experience with SoC performance modeling, virtual platforms, and executable specifications. - Hands-on experience with performance and workload benchmarking, as well as design and verification automation flows.
Nice to have
- Ph.D. in Electrical Engineering, Computer Engineering, Computer Science, or a related technical discipline. - Experience in platform design and translating customer-facing requirements into system-level requirements.
Skills: SoC architecture, workload analysis, performance modeling, HW/SW co-design
This role has been open 0 days — well below the 77-day median for SoC/Chip Architecture roles.
SoC/Chip Architecture · SOC Architecture
|
Open roles in category
473
|
Median days open
77 d
|
Median salary
$238k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Renesas Electronics | All employers we track in this specialty (473 roles · 67 employers) |
|---|---|---|
| Open roles in this specialty | 17 | 473 |
| Open roles in the wider Digital Design & Verification family | 83 | 3322 · 115 employers |
| Median days open | 77 d | 77 d (same as this employer) |
| Median salary (USD postings) | — | $238k |
Skills observed across this category: SoC architecture, workload analysis, performance modeling, HW/SW co-design
Who's hiring in this category
- Qualcomm · 79 open roles · median 86 d
- NVIDIA · 53 open roles · median 72 d
- Apple · 37 open roles · median 15 d
- AMD · 35 open roles · median 72 d
- Arm Holdings · 27 open roles · median 120 d
- Micron Technology · 21 open roles · median 99 d
How we counted: 473 open SoC/Chip Architecture (SOC Architecture) roles from 67 employers tracked in the SemiconductorJobs index, counted 23 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.