Director, Physical Design - San Jose, California, United States
$209,500 - $299,200 USD yearly
Originally posted 7 July 2026 by the employer.
About the role
In this role, you will own complex SOC and block-level implementation challenges end-to-end—from floorplan and power intent through final signoff—while actively shaping the evolution of ML/AI-driven implementation flows. Technical scope spans multi-million instance SOC designs, advanced node signoff, and deployment of optimization engines like Synopsys DSO.ai and Cadence Cerebrus.
What you'll do
- Own floorplan architecture, power domain partitioning, and block-level implementation through synthesis, place-and-route, CTS, and ECO closure. - Drive full signoff closure across multi-corner multi-mode STA, static and dynamic IR drop, electromigration, DRC/LVS, and antenna rules. - Champion the integration of ML/AI-based optimization engines, congestion modeling, and timing prediction into production PnR flows. - Lead cross-functional convergence on timing, power, and area (PPA) targets in collaboration with RTL, DFT, packaging, and analog teams. - Define physical design guidelines, author SDC/UPF constraints, and build automated design metric and data collection pipelines. - Mentor and technically guide a team of 3–8 physical design engineers across multiple concurrent tapeouts.
What you'll need
- Master’s degree in Electrical Engineering, Computer Engineering, or a related discipline with 15+ years of industry experience in physical design or SoC backend implementation. - 4+ years of technical lead experience owning complex physical design delivery, alongside 3+ successful tapeouts at 7nm or below. - 5+ years of SoC-level floorplanning, top-level integration, and full-chip physical implementation. - 10+ years of hands-on experience with Synopsys Fusion Compiler or Cadence Innovus, and 8+ years of STA closure using Synopsys PrimeTime. - 5+ years of power integrity signoff using Ansys RedHawk or Cadence Voltus, and multi-voltage design experience using UPF/CPF. - 5+ years of physical verification signoff using Mentor Calibre DRC/LVS. - 8+ years of Tcl scripting, 3+ years of Python/Perl automation, and 2+ years applying ML/AI-driven physical design tools such as Synopsys DSO.ai or Cadence Cerebrus.
Nice to have
- Experience with FPGA or structured-ASIC fabric implementation. - Exposure to 3DIC / chiplet integration including UCIe, EMIB, and hybrid bonding constraints. - Prior work on high-speed I/O integration such as PCIe Gen 5/6, HBM PHY, and SerDes. - Experience with formal verification handoff flows and CDC/RDC methodology integration. - Contributions to EDA vendor beta programs, academic publications, or conference presentations (DAC, ICCAD, SLIP).
Skills: Physical Design, floorplan, place-and-route, signoff closure, ML/AI-driven flows
This role has been open 106 days — well above the 61-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
656
|
Median days open
61 d
|
Median salary
$187k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Altera | All employers we track in this specialty (656 roles · 79 employers) |
|---|---|---|
| Open roles in this specialty | 13 | 656 |
| Open roles in the wider Physical Implementation family | 27 | 1464 · 110 employers |
| Median days open | 96 d | 61 d (+35 d vs this employer) |
| Median salary (USD postings) | — | $187k |
Skills observed across this category: Physical Design, floorplan, place-and-route, signoff closure, ML/AI-driven flows
Who's hiring in this category
- Qualcomm · 119 open roles · median 44 d
- AMD · 61 open roles · median 26 d
- Synopsys · 38 open roles · median 35 d
- Intel Corporation · 36 open roles · median 14 d
- NVIDIA · 36 open roles · median 70 d
- Broadcom · 32 open roles · median 100 d
How we counted: 656 open Physical Design (Physical Design) roles from 79 employers tracked in the SemiconductorJobs index, counted 21 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.