Originally posted 10 November 2026 by the employer.
About the role
This role owns test engineering and test automation across wafer, component, and system levels for the T100 optical processing units and POC1 units. You will define test criteria, build the test automation infrastructure and data systems, and hire and lead the test engineering team.
What you'll do
- Define and own the test strategy across wafer, component, and system levels for T100 OPU modules and POC1 units.
- Develop wafer-level probe and test programs to screen known-good die before packaging.
- Establish system-level tests verifying the optical, electrical, and computational paths produce correct results.
- Build automation across all test levels, including test sequences, probe and fixturing, instrument control, and pass criteria.
- Design test data management systems, including data schemas, volume storage, and die-level traceability through packaging.
- Hire and lead the test team while remaining hands-on at the test bench.
What you'll need
- MS or PhD in engineering, physics, or computer science with 10+ years in test engineering or test automation for hardware, including team leadership experience.
- Experience building a test automation system from scratch that supported production volume.
- Wafer-level test experience on logic or photonic devices, including probe and test program development.
- Background in system-level testing where results depend on multi-subsystem interactions.
- Experience building or owning a test data management system with die-level traceability through packaging.
- Track record connecting multi-level test data and applying AI/ML techniques to predict downstream behavior and set screening criteria.
- Strong software skills in Python or similar languages for instrument control and test framework architecture.
Nice to have
- Experience with optical or photonic test, including fiber, free-space optics, detectors, and alignment.
- High-speed electrical measurement and signal integrity experience.
- Experience with hardware-in-the-loop test frameworks.
- Background testing systems where accuracy relies on calibration rather than component tolerance.
- Experience transitioning a test process from first article into production and handing off to a contract manufacturer.
More semiconductor jobs: Test engineer jobs · Austin jobs
This role has been open 0 days — well below the 40-day median for Silicon Test Engineering roles.
Silicon Test Engineering · DFT Test
|
Open roles in category
650
|
Median days open
40 d
|
Category median salary (all employers)
$176k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Neurophos | All employers we track in this specialty (650 roles · 86 employers) |
|---|---|---|
| Open roles in this specialty | 1 | 650 |
| Open roles in the wider Silicon Validation & Test family | 2 | 2421 · 121 employers |
| Median days open | 0 d | 40 d (−40 d vs this employer) |
| Median salary (USD postings) | — | $176k |
Who's hiring in this category
- Teradyne · 87 open roles · median 39 d
- Infineon Technologies · 51 open roles · median 36 d
- Renesas Electronics · 46 open roles · median 34 d
- Texas Instruments · 33 open roles · median 46 d
- Qualcomm · 29 open roles · median 53 d
- Micron Technology · 25 open roles · median 57 d
How we counted: 650 open Silicon Test Engineering (DFT Test) roles from 86 employers tracked in the SemiconductorJobs index, counted 10 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Silicon Validation & Test family row. Figures refresh nightly.