Director of Buffer & Memory Subsystem Architecture - San Jose, CA, United States
$250,000 - $300,000 USD yearly
Originally posted 1 September 2026 by the employer.
About the role
This Director will spearhead the HW/SW co-design of HBF–xPU systems, translating AI workload traces into architectural policies for caching, prefetching, and data movement. The role demands expertise in memory controllers and performance modeling to define interface contracts and optimize system-level efficiency.
What you'll do
- Serve as the founding technical lead of the HBF R&D team, owning HW/SW architecture decisions and technical alignment.
- Lead HW/SW co-design by defining architecture, functional partitioning, and interface contracts across the HBF hardware and software stack.
- Drive HBF system optimization through memory architecture, performance modeling, and system-level implementation.
- Develop HBF system models and event-/trace-driven simulators for AI memory performance analysis.
- Analyze workload performance and optimize latency, bandwidth, and memory efficiency through architecture modeling.
- Validate architectural assumptions and provide data-driven insights for cross-functional architecture decisions.
What you'll need
- 8+ years of experience in Memory Controllers, Cache/Prefetch architectures, SSD/Storage Controllers, Accelerator Memory systems, and DMA/Data Movement architectures.
- Expertise in the development of queueing, scheduling, and buffer management algorithms.
- Strong expertise in system performance analysis, including memory latency, bandwidth, locality, contention, and Workload characterization.
- Ability to translate complex workload traces into architectural policies.
- Proven HW/SW co-design experience.
- Ability to translate AI workload, compiler, runtime, and inference-engine behavior into memory hierarchy, data-movement, prefetch, scheduling, and programming-model requirements.
- Experience owning system architecture decisions, technical requirements, interface definitions, and performance acceptance criteria across multiple hardware and software components.
- Experience defining functional partitioning and interface contracts across hardware, firmware, drivers, compiler/runtime, and application software.
- Experience developing or extending simulation tools for architectural modeling using Python, C/C++, SystemC, or comparable modeling environments, including event-driven, trace-driven, or queueing-based models.
Skills: memory controllers, performance modeling, memory architecture, HW/SW co-design, AI memory performance analysis, buffer management algorithms
This role has been open 33 days — well below the 69-day median for Memory Design roles.
Memory Design · Memory Design
|
Open roles in category
287
|
Median days open
69 d
|
Median salary
$205k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | SK Hynix America | All employers we track in this specialty (287 roles · 29 employers) |
|---|---|---|
| Open roles in this specialty | 5 | 287 |
| Median days open | 68 d | 69 d (−1 d vs this employer) |
| Median salary (USD postings) | — | $205k |
Skills observed across this category: memory controllers, performance modeling, memory architecture, HW/SW co-design, AI memory performance analysis, buffer management algorithms
Who's hiring in this category
- Micron Technology · 151 open roles · median 86 d
- Synopsys · 27 open roles · median 49 d
- SanDisk · 17 open roles · median 32 d
- Broadcom · 16 open roles · median 50 d
- Qualcomm · 12 open roles · median 149 d
- NVIDIA · 7 open roles · median 59 d
How we counted: 287 open Memory Design (Memory Design) roles from 29 employers tracked in the SemiconductorJobs index, counted 5 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Figures refresh nightly.