Director of 3D Stacked Logic Design - San Jose, CA, United States
$250,000 - $300,000 USD yearly
Originally posted 3 September 2026 by the employer.
About the role
This role leads the design and implementation of high-speed digital IP for 3D-stacked DRAM peripheral circuits and DFT, driving co-development initiatives with U.S.-based customers to enable DRAM-on-Logic system configurations. The position focuses on strengthening market leadership through advanced digital IP design and delivering comprehensive services that support the co-design of 3D-stacked DRAM logic dies.
What you'll do
- Lead the design of high-speed digital IP for 3D-stacked DRAM peripheral circuits and DFT (including RTL design to implementation).
- Drive foundry verification of service-ready IPs and infrastructure setup for IP business.
- Deliver services to ensure seamless IP integration in customer design environments.
- Strengthen leadership in the DRAM-on-Logic era through advanced digital IP design for 3D-stacked DRAM.
- Provide digital IP services for 3D-stacked DRAM to enable DRAM-on-Logic system configurations for customers.
- Co-design 3D-stacked DRAM logic die with U.S.-based customers.
What you'll need
- Bachelor’s degree or higher in Electrical Engineering or a related discipline.
- Development of Digital Logic IP/SoC based on Hardware Description Languages (Verilog, VHDL).
- 8+ years of relevant experience in RTL design and implementation memory PHY, hard macro IP for high-speed circuit, or high-speed digital IP design.
- Experience in memory controller.
- Experience in memory Built-in Self Test (BIST), DRAM Design for Test (DFT) / Design for Debug (DFD).
- Deep understanding of PPA analysis and optimization, and physical design.
Skills: 3D-stacked DRAM logic design, digital IP design, RTL design to implementation, memory controller, DRAM Design for Test (DFT)
This role has been open 41 days — well below the 61-day median for Digital/RTL Design roles.
Digital/RTL Design · RTL Design
|
Open roles in category
1021
|
Median days open
61 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | SK Hynix America | All employers we track in this specialty (1021 roles · 103 employers) |
|---|---|---|
| Open roles in this specialty | 1 | 1021 |
| Open roles in the wider Digital Design & Verification family | 1 | 3188 · 115 employers |
| Median days open | 41 d | 61 d (−20 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: 3D-stacked DRAM logic design, digital IP design, RTL design to implementation, memory controller, DRAM Design for Test (DFT)
Who's hiring in this category
- Qualcomm · 134 open roles · median 64 d
- Synopsys · 86 open roles · median 29 d
- AMD · 72 open roles · median 35 d
- Analog Devices · 49 open roles · median 47 d
- NVIDIA · 46 open roles · median 63 d
- NXP Semiconductors · 41 open roles · median 84 d
How we counted: 1021 open Digital/RTL Design (RTL Design) roles from 103 employers tracked in the SemiconductorJobs index, counted 15 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.