Director FPGA Silicon Design Engineering - CA, San Jose, United States
Digital Design & SoC Architecture
Originally posted 31 August 2026 by the employer.
About the role
What you'll do
- Lead FPGA configuration architecture, including bitstream formats, boot flows, interfaces, reliability, and scalability.
- Establish long-term architectural vision and roadmap for configuration, PR, readback, debug, and observability capabilities.
- Lead innovation in runtime reconfiguration technologies for adaptive, high-availability systems.
- Drive system-level trade-offs across configuration bandwidth, latency, power, memory hierarchy, and interconnect architecture.
- Lead development of architecture specifications and guide implementation teams through execution and productization.
What you'll need
- Experience in FPGA, ASIC, or SoC architecture with significant technical leadership responsibilities.
- Familiarity with FPGA toolchains, including synthesis, place-and-route, implementation, and PR flows.
- Experience leading architecture teams and driving large cross-functional initiatives from concept through product release.
- Strong understanding of modern silicon architectures, chiplet-based systems, memory hierarchies, and high-speed interconnects.
- BS, MS, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related discipline.
Market context
This role has been open 44 days — well below the 56-day median for FPGA Design roles.
FPGA Design · RTL Design
|
Open roles in category
104
|
Median days open
56 d
|
Median salary
$162k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | AMD | All employers we track in this specialty (104 roles · 27 employers) |
|---|---|---|
| Open roles in this specialty | 12 | 104 |
| Median days open | 48 d | 56 d (−8 d vs this employer) |
| Median salary (USD postings) | — | $162k |
Who's hiring in this category
- Altera · 29 open roles · median 57 d
- AMD (this employer) · 11 open roles · median 51 d
- Teradyne · 10 open roles · median 66 d
- Qualcomm · 8 open roles · median 38 d
- Microchip Technology · 6 open roles · median 89 d
- Keysight Technologies · 5 open roles · median 6 d
How we counted: 104 open FPGA Design (RTL Design) roles from 27 employers tracked in the SemiconductorJobs index, counted 14 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Figures refresh nightly.