Director Design Engineering - Richardson, Texas, United States of America
$191,000 - $332,000 USD yearly
Originally posted 26 October 2026 by the employer.
About the role
As Director of Design Engineering, you will lead the development and execution of complex SoC programs across advanced semiconductor technologies. You will oversee front-end design methodology and architectural execution to deliver silicon solutions from concept through tape-out and productization.
What you'll do
- Lead design and execution for complex SoC, AI/ML, networking, compute, or edge-processing products. - Guide front-end engineering spanning architecture definition, RTL implementation, integration, synthesis, timing closure, and tape-out readiness. - Balance performance, power, area (PPA), reliability, manufacturability, and product cost across multi-disciplinary design teams. - Oversee organizational capabilities across architecture, RTL, integration, verification, DFT, physical design, and silicon bring-up. - Partner across architecture, packaging, software, product engineering, foundry, and operations while interfacing with customers, IP providers, and EDA vendors. - Drive adoption of design strategies including chiplet integration, 2.5D/3D packaging, and low-power architectures.
What you'll need
- Bachelor's, Master's, or Ph.D. in Electrical Engineering, Computer Engineering, or a related field. - 15 years of semiconductor design experience with progressive technical and leadership responsibility. - 8 years of engineering management experience leading senior technical teams. - Proven track record of delivering multiple successful ASIC/SoC tape-outs across advanced technology nodes. - Hands-on expertise in front-end design, including RTL design and integration, microarchitecture development, synthesis, CDC/Lint, DFT, and timing closure. - Deep understanding of complete RTL-to-GDSII development flows and large-scale complex SoC designs involving multiple IPs and subsystems.
Nice to have
- Experience delivering products on advanced technology nodes (7nm, 5nm, 3nm and beyond). - Experience with AI/ML accelerators, compute platforms, networking, automotive, or high-performance computing products. - Familiarity with advanced packaging technologies including chiplets, 2.5D, and 3D integration. - Direct experience working with foundries, ecosystem partners, and technology roadmap development. - Understanding of low-power design methodologies, power management, and system-level optimization.
Skills: SoC, RTL, synthesis, timing closure, tape-out, PPA
This role has been open 0 days — well below the 65-day median for Digital/RTL Design roles.
Digital/RTL Design · RTL Design
|
Open roles in category
1077
|
Median days open
65 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | GlobalFoundries | All employers we track in this specialty (1077 roles · 103 employers) |
|---|---|---|
| Open roles in this specialty | 18 | 1077 |
| Open roles in the wider Digital Design & Verification family | 48 | 3346 · 116 employers |
| Median days open | 35 d | 65 d (−30 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: SoC, RTL, synthesis, timing closure, tape-out, PPA
Who's hiring in this category
- Qualcomm · 158 open roles · median 62 d
- Synopsys · 87 open roles · median 38 d
- AMD · 77 open roles · median 44 d
- Analog Devices · 49 open roles · median 55 d
- NXP Semiconductors · 42 open roles · median 94 d
- NVIDIA · 36 open roles · median 51 d
How we counted: 1077 open Digital/RTL Design (RTL Design) roles from 103 employers tracked in the SemiconductorJobs index, counted 26 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.