Digital Verification Apprenticeship
Originally posted 19 September 2026 by the employer.
About the role
This apprenticeship involves developing and maintaining verification environments for digital design blocks and systems. You will apply UVM methodology to build reusable and scalable verification components.
What you'll do
- Develop verification environments for digital design blocks and systems using industry-standard methodologies.
- Design and execute testbenches using Verilog and SystemVerilog, applying UVM methodology.
- Work with design and architecture teams to develop test plans and functional coverage models.
- Analyze simulation results, debug failures, and identify design or verification issues.
- Implement SystemVerilog Assertions (SVA) to verify design behavior and protocol compliance.
- Contribute to regression execution, coverage analysis, and documentation of verification plans and results.
What you'll need
- Completed B.E/B.Tech in Electronics and Communication Engineering or a related field.
- Strong knowledge of Verilog and SystemVerilog programming languages.
- Familiarity with UVM-based verification methodology and its practical applications.
- Solid understanding of digital design and digital verification concepts and flows.
- Ability to write and debug SystemVerilog Assertions (SVA).
Nice to have
- Awareness of MIPI protocols (UniPro and M-PHY).
- Exposure to simulation tools, regression environments, code coverage, and functional coverage analysis.
Skills: verification environments, testbenches, Verilog and SystemVerilog, UVM methodology, SystemVerilog Assertions (SVA), functional coverage
This role has been open 10 days — well below the 63-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1166
|
Median days open
63 d
|
Median salary
$192k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Synopsys | All employers we track in this specialty (1166 roles · 95 employers) |
|---|---|---|
| Open roles in this specialty | 66 | 1166 |
| Open roles in the wider Digital Design & Verification family | 151 | 3112 · 115 employers |
| Median days open | 23 d | 63 d (−40 d vs this employer) |
| Median salary (USD postings) | — | $192k |
Skills observed across this category: verification environments, testbenches, Verilog and SystemVerilog, UVM methodology, SystemVerilog Assertions (SVA), functional coverage
Who's hiring in this category
- Qualcomm · 99 open roles · median 55 d
- AMD · 97 open roles · median 41 d
- NVIDIA · 83 open roles · median 70 d
- Synopsys (this employer) · 63 open roles · median 23 d
- SiFive · 56 open roles · median 54 d
- Micron Technology · 53 open roles · median 113 d
How we counted: 1166 open Design Verification (Design Verification) roles from 95 employers tracked in the SemiconductorJobs index, counted 1 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.