Synthesis & STA Engineer – High-Speed SerDes - San Jose, California, United States

Originally posted 14 September 2026 by the employer.

Work on high-speed analog/mixed-signal SerDes and connectivity ASICs.

About the role

As a Synthesis & STA Engineer – High-Speed SerDes, you will drive planning, coordination, and execution supporting the design of Astera Labs' high-speed analog/mixed-signal SerDes and connectivity ASICs. This role requires end-to-end ownership of logic synthesis and static timing analysis across the digital portions of mixed-signal SerDes PHY designs at advanced nodes.

What you'll do

• Perform RTL synthesis, driving area, power, and timing optimization for digital controller and DSP blocks within high-speed SerDes PHY designs.
• Author, develop, and validate SDC constraints from scratch, including clock definitions, generated clocks, multi-frequency/multi-mode constraints, I/O delays, false paths, multicycle paths, and clock-domain crossing exceptions.
• Set up and manage MMMC (Multi-Mode Multi-Corner) environments to enable accurate and efficient STA across process, voltage, and temperature (PVT) corners.
• Drive timing closure from synthesis through sign-off, ensuring robust timing across digital blocks embedded within analog/mixed-signal SerDes IP and full-chip SoC integration.
• Apply advanced sign-off methodologies at TSMC 5nm/3nm and below, including OCV/AOCV/POCV and PVT effects relevant to high-speed serial link performance.
• Leverage ETM/ILM libraries for hierarchical timing analysis and correlation of SerDes hard-macro blocks.

What you'll need

• Bachelor's in Electrical Engineering or Computer Science; Master's preferred.
• ≥8 years of experience in synthesis, timing constraints development, STA, and sign-off for high-speed mixed-signal IP in Server, Storage, Networking, or SerDes applications.
• Strong proficiency in writing and debugging SDC constraints, with deep understanding of clock modeling, generated clocks, clock-domain crossings, and exception handling.
• Expertise in STA methodology and timing closure at both block and full-chip level using Synopsys PrimeTime and/or Cadence Tempus.
• Strong knowledge of synthesis, place-and-route, extraction, and equivalence checking flows (Formality/Conformal) in advanced nodes (5nm/3nm and below).
• Proficiency with Cadence and/or Synopsys physical design/STA toolchains.
• Strong scripting ability (Tcl, Python, Perl).

Nice to have

• Direct experience with high-speed SerDes, Ethernet PHY (112G/224G), or PCIe/CXL PHY digital controller and DSP timing challenges.
• Understanding of analog/mixed-signal integration concerns, including analog-digital interface timing, PLL/DLL/CDR clock structures, and level-shifter/isolation cell constraints.
• Knowledge of ECO methodologies, DFT tools, and test coverage analysis for mixed-signal designs.
• Experience working with IP vendors for both RTL and hard-macro integration, including Liberty (.lib), LEF, and behavioral model characterization.
• SystemVerilog/Verilog proficiency.
• Familiarity with power-aware synthesis and STA (UPF/CPF flows).
• Experience with high-speed clocking architectures and multi-rate clock domain management typical in SerDes designs.