Digital/Mixed Signal Modeling/Verification Engineer - Sunnyvale, United States
Originally posted 14 September 2026 by the employer.
This role involves RNM/SystemVerilog behavioral modeling and verification of analog/RF blocks like regulators, bandgaps, and data converters within a large SoC.
About the role
This role involves verifying the functionality and performance of Apple's SOCs. You will own RNM/SystemVerilog behavioral modeling and verification of analog/RF blocks inside a large SoC.
What you'll do
- Own RNM/SystemVerilog behavioral modeling and verification of analog/RF blocks (regulators, bandgaps, data converters, LNA/PA, mixers, PLLs) inside a large SoC. - Develop self-checking models for analog/RF blocks. - Create assertions for analog/digital specifications. - Set up AMS environments with analog designers.
What you'll need
- BS and a minimum of 10 years relevant industry experience. - Strong fundamentals in analog/RF circuit theory/topologies. - Expert in RNM coding in SystemVerilog.
Nice to have
- MSc and 7 years of relevant industry experience. - Experience working with Cadence mixed signal verification environment. - Ability to read analog schematics and extract related main functionality. - Experience modeling mixed signal/RF blocks including biasing networks, power regulators, bandgaps, Opamp's, OTA's, data converters, LNA, PA, mixers, couplers, splitters, combiners. - Experience modeling high frequency PLL's.
Skills: mixed signal verification, SystemVerilog, analog/RF circuit theory, Cadence mixed signal verification environment, modeling mixed signal/RF blocks
This role has been open 30 days — well below the 65-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1192
|
Median days open
65 d
|
Median salary
$186k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Apple | All employers we track in this specialty (1192 roles · 95 employers) |
|---|---|---|
| Open roles in this specialty | 19 | 1192 |
| Open roles in the wider Digital Design & Verification family | 64 | 3191 · 115 employers |
| Median days open | 23 d | 65 d (−42 d vs this employer) |
| Median salary (USD postings) | — | $186k |
Skills observed across this category: mixed signal verification, SystemVerilog, analog/RF circuit theory, Cadence mixed signal verification environment, modeling mixed signal/RF blocks
Who's hiring in this category
- Qualcomm · 106 open roles · median 42 d
- AMD · 99 open roles · median 55 d
- NVIDIA · 82 open roles · median 57 d
- Synopsys · 63 open roles · median 30 d
- SiFive · 54 open roles · median 72 d
- Cadence Design Systems · 50 open roles · median 114 d
How we counted: 1192 open Design Verification (Design Verification) roles from 95 employers tracked in the SemiconductorJobs index, counted 15 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.