Originally posted 31 August 2026 by the employer — open 21 days.
Join the team delivering digital controller IP for power, clock, and error management subsystems within the onsemi Treo™ platform.
About the role
This role is for a senior Digital Design Member of Technical Staff (MTS) to lead and deliver digital controller IP for power, clock, and error management subsystems. You will focus on architecting, designing, integrating, and evolving complex digital IP that tightly interfaces with analog and mixed-signal blocks in automotive-grade SoCs for the Treo™ platform.
What you'll do
- Architect, design, and implement digital system controllers for power management, clock management, and error detection, reporting, and mitigation subsystems.
- Develop robust digital IP that controls and interacts closely with analog and mixed-signal blocks.
- Own IP delivery from architecture through RTL, verification, integration, and silicon bring-up support.
- Drive and support digital-on-top product integration flows, including IP integration into SoC environments, clocking, reset, power domain, and safety integration.
- Ensure designs meet automotive functional safety requirements (e.g., ISO 26262 concepts such as ASIL, fault coverage, diagnostic mechanisms).
- Mentor and technically guide junior and mid-level engineers, promoting best practices in design, documentation, and review culture.
What you'll need
- 15+ years of hands-on digital design experience, primarily in ASIC or SoC development.
- Proven experience delivering automotive IP with functional safety requirements.
- Strong background designing digital controllers for analog blocks (e.g., power regulators, PLLs, sensors, clocking systems).
- Deep understanding of system-level digital integration, including power and clock domain management, reset strategies, and error handling and safety mechanisms.
- Solid experience with RTL design (SystemVerilog).
- Working knowledge of constrained-random verification methodologies, including SystemVerilog and UVM.
Nice to have
- Experience with automotive safety standards such as ISO 26262 (concept, system, or IP-level application).
- Working knowledge of JIRA for task tracking and JAMA for requirements management.
- Exposure to safety diagnostics, fault injection, or safety verification techniques.
- Familiarity with low-power design techniques and power-aware verification.
Skills: digital architecture, RTL, synthesis, timing analysis, power management ICs, mixed-signal
This role has been open 20 days — well below the 62-day median for Digital/RTL Design roles.
Digital/RTL Design · RTL Design
|
Open roles in category
938
|
Median days open
62 d
|
Median salary
$184k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | onsemi | All employers we track in this specialty (938 roles · 101 employers) |
|---|---|---|
| Open roles in this specialty | 32 | 938 |
| Open roles in the wider Digital Design & Verification family | 55 | 3017 · 114 employers |
| Median days open | 95 d | 62 d (+33 d vs this employer) |
| Median salary (USD postings) | — | $184k |
Skills observed across this category: digital architecture, RTL, synthesis, timing analysis, power management ICs, mixed-signal
Who's hiring in this category
- Qualcomm · 143 open roles · median 54 d
- AMD · 61 open roles · median 62 d
- Synopsys · 57 open roles · median 30 d
- NXP Semiconductors · 51 open roles · median 68 d
- NVIDIA · 48 open roles · median 45 d
- Analog Devices · 39 open roles · median 74 d
How we counted: 938 open Digital/RTL Design (RTL Design) roles from 101 employers tracked in the SemiconductorJobs index, counted 21 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.